Hi Rathna, It looks like Nilay has answered your question, but please let me know if you need any more help. I would be happy to help you, especially since you are from the greatest university in the country! (I'm a U.C. graduate as well) :)
Brad > -----Original Message----- > From: [email protected] [mailto:m5-users- > [email protected]] On Behalf Of Nilay Vaish > Sent: Wednesday, February 23, 2011 1:54 PM > To: M5 users mailing list > Subject: Re: [m5-users] help reg Interconnection in M5 > > On Wed, 23 Feb 2011, RATHNA KEERTHI wrote: > > > Hello all, > > > > I am Rathna, Graduate student at University of Cincinnati. I am > > currently using M5 to do my Master's Thesis. I am new to M5. > > > > I wanted to know about the current status of integration of RUBY > > memory model from GEMS into M5? > > > > Also does Alpha processor of M5 only supports BUS Interconnect? or can > > it be modified to a Ring or Mesh network? > > > > Thank you very much for your time and help. > > > > Sincerely, > > Rathna > > > > You can configure ruby to use the mesh interconnect. You would need to > specify the topology, and a couple of other parameters. Some thing like > following would work - > > ./build/ALPHA_SE_MOESI_hammer/m5.fast ./configs/example/ruby_se.py - > n 8 --topology Mesh --mesh-rows 2 --num-l2cache 8 --num-dir 8 > > > -- > Nilay > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
