Hello,
I have a thread migration system set up where I can switch back and
forth between separate cores anytime want. I have two separate lists of
cpus, one all simple timing and the other O3. I drop out of the
simulation anytime I want to switch to the O3 core or back to the simple
timing, call m5.drain(), m5.switchCpus(), and m5.resume(). Now I want to
model the migration effects. I was thinking of clearing the caches using
functional accesses and then invalidating everything that was written
back, and also clearing other processor state such as tlbs and branch
predictors similar to what was suggest by Rick Strong in this thread:
http://www.mail-archive.com/[email protected]/msg01993.html
I was just curious if anybody has done this and if so how they modelled
this. Also any suggestions on how can thread context migration, mainly
register migration, be modelled? I was thinking to modelling this by
saving the thread context in some global thread context object, then
immediately reading it back over a bus after a switch.
-Tony
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