On Fri, 04 Mar 2011 16:55:33 +0200, "Ioannis E. Venetis"
<[email protected]> wrote:
Dear all,
Lately I have been looking for a simulator that would support
multi-core
and/or SMT on each core. From what I have seen and the documents I
have
read, M5 seems to support this. I managed to download and compile M5
and
run the basic tests that are included, but now I have come to the
point
where I have some questions in order to move further. Hopefully these
questions will be answered here! By the way, I am interested in the
Alpha architecture that is supported.
1) Which Alpha processor is actually simulated (EV4, EV45, EV5, EV56,
...)? Is only the basic Alpha instruction set supported or also some
of
the extensions (BWX, MVI, FIX, CIX)? From the download page I see
that a
cross-compiler for EV67 is used, but some discussions on the mailing
lists say that CIX (and MIV?) are not supported. These discussions
are
1.5 year old. Has something changed since then?
I believe all Alpha instructions are supported. We simulate the user
visible context of an EV6, but we run EV5-like palcode.
2) Up to which glibc can we use when compiling applications to run on
M5? Again I see a version of 2.6.1, but with crosstool-ng we can
compile newer versions. Are they supported?
Hopefully any version should work, although you might run into function
or two that isn't implemented.
3) It is not clear to me how to enable multiple cores and/or SMT when
using M5. Is this done during compilation or when starting a Python
script? Are there any examples I could study to see how this is done?
Can we combine multiple cores with SMT on each core? Again, any
examples how to do this? Can we run such applications in either mode
(FS or SE)?
Multiple cores work in either mode. SMT currently only works is SE
mode. You can look at the regression tests in the tests dir for some
examples of a multi-core system and an MT system. SMT support might be a
bit rusty.
4) In a rather old post on the mailing list I read that up to 64
cores
could be supported in Full System simulation mode and virtually as
many
cores as we like in Syscall emulation mode. Does this still hold?
Yes.
5) Is it possible to run a multi-threaded application on the M5
simulator? In other words, if I have an application implemented using
POSIX threads, can I compile it with my cross-compiler and run it on
the M5 simulator? Will multiple threads be created and assigned to
the
simulated cores? I am not asking whether M5 itself will run in
parallel, but if the simulated application will run in "parallel" on
the multiple simulated cores. If using POSIX threads is not
supported,
is there any other way to do it?
Yes, you could run it on top of Linux or you could take a look at the
m5 threads library. I'm not sure what state it's in for Alpha, but I
belive it works for x86 and sparc. In the case of FS, the Linux
scheduler will make whatever decisions it wants and you can have more
threads than cores. For SE mode you can't have more threads than cores.
Ali
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