Once a block is invalidated the cache doesn't care what the tag is. You'd have to modify the writeback miss code to detect the case where there's an invalid block in the set that has a tag match.
(Assuming you're talking about the traditional m5 caches and not Ruby.) Steve On Mon, Mar 7, 2011 at 9:00 PM, Stevenson Jian <[email protected]>wrote: > Hi everyone, > Could someone tell me if the following behavior is correct on m5? > 1)L2 has address XX in way n. > 2)L1 accesses address XX in way n. > 3)L1 writes to address XX. > 4)way n in L2 is invalidated. > 5) when L1 evicts address XX, it is written to a new way, way m, in l2 > where m!=n. > > If this behavior is indeed correct, could I modify the code so that in step > 5) L1 writes back to way n in L2? Would that break some code elsewhere? > Thanks! > Steve > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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