The cache is prepopulated with invalid blocks whose contents should never be read (because they should be written to the first time they're used).
Steve On Tue, Mar 8, 2011 at 4:58 PM, Adam Jacobvitz <[email protected]> wrote: > Okay, so what if there never was a block in that set (e.g. its the first > time any block ever is being inserted into the set)? Does it just return a > hex value corresponding to whatever garbage value was in that memory > location? > > By the way, thanks for the help, and thanks for making M5! > > Adam > > > On 3/8/2011 7:18 PM, Steve Reinhardt wrote: > >> findVictim() will return an invalid block to be written to without doing >> an unnecessary replacement. >> >> On Tue, Mar 8, 2011 at 4:03 PM, Adam Jacobvitz <[email protected] <mailto: >> [email protected]>> wrote: >> >> So how do you handle the first write into the cache before there >> is anything to replace? I'm also noticing a lot of "misses" in the >> caches for which there is no replacement event. >> >> Thanks, >> >> Adam >> >> On 3/8/2011 6:42 PM, Steve Reinhardt wrote: >> >> >> >> On Tue, Mar 8, 2011 at 10:07 AM, Adam Jacobvitz <[email protected] >> <mailto:[email protected]> <mailto:[email protected] >> >> <mailto:[email protected]>>> wrote: >> >> Two Questions: >> >> 1) How are blocks written into the L1 or L2 cache when >> there is no >> block to replace? I see this thing called a "tempBlock" but I >> can't seem to find the code that writes it into the cache... >> >> >> It isn't written in... that's the point, if there's no block >> to replace, then you can't write it into the cache. In >> practice I don't know if that ever happens though. >> >> 2) In the M5 Cache structure (not Ruby) I can't seem to >> find any >> notion of a "way". Does the cache structure know what a >> "way" is? >> >> >> Not really, the code is organized based on sets rather than >> ways. See src/mem/cache/tags/cacheset.hh. >> >> Steve >> >> >> Thanks! >> >> -- Adam Jacobvitz >> Graduate Student >> Duke Computer Architecture Group >> Electrical and Computer Engineering Department >> Duke University, North Carolina >> http://arch.cs.duke.edu/ >> _______________________________________________ >> m5-users mailing list >> [email protected] <mailto:[email protected]> >> <mailto:[email protected] <mailto:[email protected]>> >> >> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] <mailto:[email protected]> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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