Hi Nilay, I'd like to use inclusive caches in M5. So I followed your instructions about how to use MESI_CMP_directory in ruby. I have run the "hello world" test code successfully. I have some questions as below:
1/ MESI_CMP_directory is an inclusive cache coherence protocol, is that right? 2/ Is ruby the only way to run M5 with inclusive cache supported? Before my running M5 with option 'RUBY=True', I use ./build/ALPHA_SE/m5.opt with se.py script file and eio supported to run M5 with eio traces. If I want to make sure the cache hierarchy be inclusive, I have to move everything needed to Ruby, with specific protocols, is that correct? 3/ I noticed that only TimingSimpleCPU supported in Ruby now. Does that mean the processor is not Out of Order? If so, is it possible to use OoO CPU? 4/ Since the baseCache in ruby is rubyCache, I modified rubyCache configuration exactly as what I did before in BaseCache. However, in the output file 'config.ini', I cannot see the changes. Files I modified about caches are configs/common/Caches.py and src/mem/ruby/system/Cache.py. Are there any more files I need to modify about cache implementation? Thank you in advance. Best, Yingying On Tue, Feb 22, 2011 at 7:14 AM, Nilay <[email protected]> wrote: > > On Tue, February 22, 2011 6:13 am, sunitha p wrote: > > Hi all, > > > > Default M5 uses MOESI cache coherence protocol which satisfies exclusive > > property between the cache levels. > > > > M5 even supports MESI protocol. Does this protocol support inclusive > > property,... because in the files related to MESI , > > > > i found some comment lines as inclusive.... > > > > Since the code is not in C++..am not able to understand the flow of > > instructions...if inclusive...? > > > > kindly help > > > > thanks > > > > -- > > Sunitha.P > > 9092892876 > > _______________________________________________ > > m5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > If you are talking about the MESI CMP directory protocol, then it is true > that the L2 cache contains that L1 cache entries. > > > -- > Nilay > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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