SE mode has a page table and TLBs, so it shouldn't be too hard to put per-page uncacheable bits in there that are handled the same as in FS mode. The page table structure is defined in src/mem/page_table.*. At runtime it's managed via the Process class, in src/sim/process.*.
Steve On Thu, Mar 24, 2011 at 10:07 AM, Michael Levenhagen <[email protected]> wrote: > Hello, > > I've incorporated parts of m5 into Sandia Lab's Structural Simulation Toolkit > (SST). > I can run a simple alpha executable in system emulation mode within SST. > I've also created a simple io_device and mapped it into my test apps memory > space. > > My question is how would I correctly set a region of physical memory to > UNCACHEABLE with write combining? > I understand that given I'm running in system emulation mode what I want to > do is probably not supported. > I'm just looking for an idea of where to start looking in the code. > > Mike > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
