Also, can somebody explain the drain functionality in a little more depth.
-Tony _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
I am having a problem switching from an O3 CPU to a TimingSimpleCPU.
There are cases I am encountering where there are instructions remaining
in certain structures in the pipeline after drain. The assertion failure
I'm encountering is Assertion `instList[0].empty()' failed. During the
mem_dep_unit switchout function. It seems the cpu is in IDLE state when
it enters drain, and thus returns immediately. The instruction that is
remaining in the mem_dep_unit is an uncacheable load and so it gets sent
directly to commit before it's handled. My question is how should drain
be handling this? Should the uncacheable load be removed from the
mem_dep_unit when it's sent to commit? Also, if I change which cycle I
do the switchout I can avoid this case but run in to another case of
Assertion `!loadQueue[i]' failed. I always seem to get one of this
assertion failures no matter when I switch. Does anybody have any ideas
on why this may be happening?
- [m5-users] Switching from an O3 core to a TimingSimple c... Anthony Gutierrez
- Re: [m5-users] Switching from an O3 core to a Timin... Ali Saidi
- Re: [m5-users] Switching from an O3 core to a Timin... Anthony Gutierrez
- Re: [m5-users] Switching from an O3 core to a Timin... Anthony Gutierrez
- Re: [m5-users] Switching from an O3 core to a T... Korey Sewell
