Hi Ali, After editing .config, removing all MPs & PBX only with above mentioned options, The kernel starts but M5 throws warnings and hangs or end up with error when I tried some different config. M5 Log: ------------------------------------------ **** REAL SIMULATION **** info: Entering event queue @ 0. Starting simulation... warn: The clidr register always reports 0 caches. For more information see: http://www.m5sim.org/warn/23a3c326 warn: The csselr register isn't implemented. For more information see: http://www.m5sim.org/warn/c0c486b8 warn: Need to flush all TLBs in MP For more information see: http://www.m5sim.org/warn/6cccf999 warn: The ccsidr register isn't implemented and always reads as 0. For more information see: http://www.m5sim.org/warn/2c4acb9c warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb 1322212000: system.terminal: attach terminal 0 warn: instruction 'mcr dccimvac' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr icimvau' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb *<hangs here>* ------------------------------------------ on m5term ------------------------------------------ ==== m5 slave terminal: Terminal 0 ==== Linux version 2.6.38-08261-g4047185 (root@mahdi-OptiPlex-755) (gcc version 4.5.1 (Sourcery G++ Lite 2010.09-50) ) #13 Fri Mar 25 20:45:22 MST 2011 CPU: ARMv7 Processor [350ff000] revision 0 (ARMv7), cr=10c53c7f CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache Machine: ARM-RealView PBX Ignoring unrecognised tag 0x00000000 Memory policy: ECC disabled, Data cache writeback On node 0 totalpages: 32768 DMA zone: 256 pages used for memmap DMA zone: 0 pages reserved DMA zone: 32512 pages, LIFO batch:7 sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 pcpu-alloc: [0] 0 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 Kernel command line: earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 PID hash table entries: 512 (order: -1, 2048 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 128MB = 128MB total Memory: 126084k/126084k available, 4988k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xffc00000 - 0xffe00000 ( 2 MB) vmalloc : 0xc8800000 - 0xf8000000 ( 760 MB) lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) modules : 0xbf000000 - 0xc0000000 ( 16 MB) .init : 0xc0008000 - 0xc0021000 ( 100 kB) .text : 0xc0021000 - 0xc0278000 (2396 kB) .data : 0xc0278000 - 0xc02944e0 ( 114 kB) NR_IRQS:128 Console: colour dummy device 80x30 Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok NET: Registered protocol family 16 L2x0 series cache controller enabled l2x0: 8 ways, CACHE_ID 0xffffffff, AUX_CTRL 0xc2520fff, Cache size: 131072 B Serial: AMBA PL011 UART driver dev:uart0: ttyAMA0 at MMIO 0x10009000 (irq = 44) is a PL011 rev3 console [ttyAMA0] enabled bio: create slab <bio-0> at 0 Switching to clocksource timer3 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) IPv4 FIB: Using LC-trie version 0.409 TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table entries: 4096 (order: 2, 16384 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered UDP hash table entries: 256 (order: 0, 4096 bytes) UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) NET: Registered protocol family 1 PMU: registered new PMU device of type 0 msgmni has been set to 246 io scheduler noop registered io scheduler deadline registered (default) clcd-pl11x issp:clcd: PL111 rev1 at 0x10020000 *<hangs here>*
------------------------------------------ If I change the config it end up with error at different point. I am trying and I know you are busy but *can you please post working configuration?* Regards, Digant Desai. 480-717-7851 On Fri, Mar 25, 2011 at 18:25, Digant <[email protected]> wrote: > In realview_defconfig I changed, > MACH_REALVIEW_PBX [=y] > AEABI [=n] > but there is no change. > > On Fri, Mar 25, 2011 at 17:48, Digant <[email protected]> wrote: > >> Hi Ali, >> Thx for quick reply. >> >> tried >> realview_defconfig<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/arm/configs/realview_defconfig;h=fcaa60328051254439df8f96dc2013b8dc750a4e;hb=40471856f2e38e9bfa8d605295e8234421110dd6>with >> latest M5 codes & kernel src 2.6.38. >> >> It didn't give any error this time but, *But its not booting.M5term >> didn't display anything*... >> >> ---------------------------------------------- >> >> command line: build/ARM_FS/m5.debug -d /tmp/output configs/example/fs.py >> Global frequency set at 1000000000000 ticks per second >> info: kernel located at: /dist/m5/system/binaries/vmlinux.arm >> Listening for system connection on port 5903 >> Listening for system connection on port 3460 >> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7004 >> >> **** REAL SIMULATION **** >> info: Entering event queue @ 0. Starting simulation... >> 331775000: system.terminal: attach terminal 0 >> ---------------------------------------------- >> m5term localhost 3460 >> ==== m5 slave terminal: Terminal 0 ==== >> ---------------------------------------------- >> >> >> >> On Thu, Mar 24, 2011 at 21:30, Ali Saidi <[email protected]> wrote: >> >>> 1) Use the latest code. ARM support is in flux and rapidly evolving, you >>> shouldn't be using anything that's not the latest. >>> 2) The kernel you've got there is compiled with thumb2 instructions only. >>> I've never tried a thumb2 kernel and there is probably something about the >>> CPU coming out of reset and executing thumb2 code that is confusing it. You >>> could either compile a kernel for arm or work on detecting that case and >>> changing the processor state to thumb before you start execution. >>> >>> Ali >>> >>> On Mar 24, 2011, at 9:00 PM, Digant wrote: >>> >>> Hi all, >>> I want to run m5 in ARM fs mode. I have put kernel image with >>> thisconfiguration >>> <http://www.linux-arm.org/git?p=ael.git;a=blob_plain;f=kernel/config/2.6.35-arm1/config-2.6.35-arm1-realview-v7-smp-thumb;hb=2010q4>and >>> used the AEL cramfs from here and copied the files into 128 MB ext2 file and >>> rename it to ael-arm.ext2. >>> >>> But when I try to run it , it gives following error. >>> * >>> /opt/m5-2e1ee8ec6266# build/ARM_FS/m5.debug -d /tmp/output >>> configs/example/fs.pyM5 Simulator System >>> >>> Copyright (c) 2001-2008 >>> The Regents of The University of Michigan >>> All Rights Reserved >>> >>> >>> M5 compiled Mar 11 2011 20:00:36 >>> M5 revision Unknown >>> M5 started Mar 24 2011 18:50:52 >>> M5 executing on mahdi-OptiPlex-755 >>> command line: build/ARM_FS/m5.debug -d /tmp/output configs/example/fs.py >>> Global frequency set at 1000000000000 ticks per second >>> info: kernel located at: /dist/m5/system/binaries/vmlinux.arm >>> Listening for system connection on port 5900 >>> Listening for system connection on port 3456 >>> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 >>> **** REAL SIMULATION **** >>> info: Entering event queue @ 0. Starting simulation... >>> m5.debug: build/ARM_FS/arch/arm/predecoder.hh:120: void >>> ArmISA::Predecoder::consumeBytes(int): Assertion `offset <= >>> sizeof(MachInst)' failed. >>> Program aborted at cycle 0 >>> Aborted* >>> >>> Thank you in advance. >>> >>> Regards, >>> Digant Desai. >>> 480-717-7851 >>> >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >>> >>> >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> >> >> Regards, >> Digant Desai. >> 480-717-7851 >> >> >
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