> toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); > toFetch->decodeInfo[tid].nextNPC = inst->branchTarget() + > sizeof(TheISA::MachInst); > toFetch->decodeInfo[tid].branchTaken = inst->readNextPC() != > (inst->readPC() + sizeof(TheISA::MachInst));
Can you try to provide a trace that will show the incorrect behavior? Maybe you can add a DPRINTF(Decode, "Squash branchTaken=%i nextPC=%x compared to %x\n", inst->branchTarget, <etc.>) and then rerun with the Decode traceflag on? At first glance, I think the code is correct because once a branch is resolved then it will update the nextPC in the actual instruction. So inst->readNextPC() *should* give you the branch target after the branch is resolved. So to check to see if it was taken or not you would need to check against the original PC + the size of instruction. Does that make sense? So then the only question now is to ask if the branch instruction was resolved (and updated in the instruction) prior to calling that squash function. If it has been, the code looks good to me. -- - Korey _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
