Is a Snoopy Cache Coherence Protocol with cache-to-cache transfer as in Illinois protocol implemented in M5?
I need such a multi-processor system where a block can be transferred from one processor's l1 cache to other processor's l1 cache. I was looking into the documentation and source code but I am totally confused. Can someone please help me to build such a system, if such a protocol is already implemented or some steps which could help me write the protocol. I am running very late on my schedule, so I am looking for suggestions from the community. Thanking You in advance. - prasanth(IIT Delhi) _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
