Hi,
To troubleshoot an issue I've been having with measuring the base CPI
from the point of view of the L2-cache (i.e. any cycles spent on normal
execution + branch mispredictions + L1 hits and misses), I'm looking to
make the L2-cache behave as though every access to it were a hit. I
figured I'd do that by making the latency for an L2 miss the same as the
latency for an L2-hit. That might be kind of difficult to do in timing
mode since (I think?) the membus introduces a variable amount of latency
between the time the data comes back from main memory and the next bus
cycle. In particular, I'm referring to this bit of code from
calcBusTiming in bus.cc (line 148-152), which is called on recvTiming():
if (tickNextIdle < curTick()) {
tickNextIdle = curTick();
if (tickNextIdle % clock != 0)
tickNextIdle = curTick() - (curTick() % clock) + clock;
}
What I'd really like to do is to simply charge the L2 hit latency as
usual, and then fetch the data from main memory without bothering with
any latencies. So I was wondering if maybe doing a functional access
might be just what I need? I've really only worked with timing mode so
far, so I'm not sure if I've got the right idea about how functional
accesses work. I've read the wiki page on the type of memory system
accesses and they do indeed happen instantaneously, but I figured I'd
double-check to make sure there's nothing of importance I'm missing.
Cheers,
Jeroen DR
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