Hello, I am looking to do some VLIW/DSP research and had some questions regarding GEM5. Specifically, would modifying the parameters of the given in-order model such as fetch/issue width, load/store queue depth, etc. be a good enough approximation?
I realize that VLIW architectures have VLIW compilers that look for VLIW-specific optimizations and that leads me to my second concern. How does GEM5 currently compile and run applications for the given in-order model? I'm guessing it may use architecture specific cross compilers. Is it possible to modify the compiler optimizations so as to get VLIW-like (or close to) code for execution? Unfortunately, I have a feeling this will be the deal breaker since I imagine no VLIW-based compilers are available or tested. However, I wanted to ask since GEM5 has an attractive main memory model and that is vital to my research objectives. I apologize if this message is a bit uninformed. I am currently looking at a variety of simulators and trying to weigh their pros and cons, which means I have not fully dived into exploring all the details of any of them. Thank you! -Daniel _______________________________________________ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
