Re: Port Genode(13.05) to exynos4412 with Fiasco.oc(R67)

Thu, 04 Jun 2015 19:16:56 -0700 

Hi Sunyu
Thanks for your answer. We have tested your patch and it works. We have reduced a bit your patch. This is our patch: 

   diff --git a/src/kernel/fiasco/src/drivers/arm/processor-arm.cpp
   b/src/kernel/fiasco/src/drivers/arm/processor-arm.cpp
   index d9102c4..8ee9101 100644
   --- a/src/kernel/fiasco/src/drivers/arm/processor-arm.cpp
   +++ b/src/kernel/fiasco/src/drivers/arm/processor-arm.cpp
   @@ -32,7 +32,7 @@ public:
       static Cpu_phys_id cpu_id();
     };

   -INTERFACE[arm && !arm_em_tz]:
   +INTERFACE[arm && !arm_em_tz && !arm_em_ns]:

     EXTENSION class Proc
     {
   @@ -62,6 +62,22 @@ public:
         };
     };

   +INTERFACE[arm && arm_em_ns]:
   +
   +EXTENSION class Proc
   +{
   +public:
   +  enum : unsigned
   +    {
   +      Cli_mask                = Status_IRQ_disabled,
   +      Sti_mask                = Status_IRQ_disabled,
   +      Status_preempt_disabled = Status_IRQ_disabled,
   +      Status_interrupts_mask  = Status_IRQ_disabled,
   +      Status_always_mask      = 0x10 | Status_FIQ_disabled,
   +    };
   +};
   +
   +
     INTERFACE[arm && !hyp]:

     EXTENSION class Proc


Your patch runs without TrustZone and TrustZone Normal Side. Our patch 
only works on TrustZone Normal Side.
When TrustZone is enabled the IRQ are used in Normal Side and the FIQ 
are used in Secure Side. That is the reason because we adapt your patch 
to be used only on TrustZone Normal Side. We are interested to use IRQ 
and FIQ when not using TrustZone.
We are trying to use Fiasco.OC without TrustZone, but using both 
interrupts, the IRQ and FIQ. We are thinking that the problem may be in 
the GIC or the TrustZone configuration.
We have tested both patchs using Fiasco.OC(r67) with GenodeOS, and 
run/printf works fine. There is the serial output:


   Exynos4412 # bootm 0x41000000
   Boot with zImage
   Starting kernel ...

   L4 Bootstrapper
      Build: #2 Thu Jun  4 10:16:41 EDT 2015, 4.9.2
      Scanning up to 2048 MB RAM, starting at offset 32MB
      Memory size is 2048MB (40000000 - bfffffff)
      Limiting 'RAM' region   [ 40000000,  bfffffff] { 80000000} to [
   40000000,  bcffffff] { 7d000000} due to 3024 MB address limit
      RAM: 0000000040000000 - 00000000bcffffff: 2048000kB
      Total RAM: 2000MB
      Scanning
   
/home/alexy/workOS/genode/genodeos/geno-issue-48u/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
      Scanning sigma0
      Scanning genode/core
      Moving up to 6 modules behind 41100000
      moving module 02 { 4111e000-41191e0b } -> { 4120e000-41281e0b }
   [474636]
      moving module 01 { 4110c000-4111d367 } -> { 411fc000-4120d367 }
   [70504]
      moving module 00 { 4109f000-4110b0ab } -> { 4118f000-411fb0ab }
   [442540]
      moving module 05 { 41062000-4109e513 } -> { 41152000-4118e513 }
   [247060]
      moving module 04 { 41011000-41061c2f } -> { 41101000-41151c2f }
   [330800]
      moving module 03 { 41010000-4101010f } -> { 41100000-4110010f } [272]
      Loading no-issue-48u/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
      Loading sigma0
      Loading genode/core
      find kernel info page...
      found kernel info page at 0x40002000
   Regions of list 'regions'
        [ 40000000,  40000167] {      168} Root   mbi_rt
        [ 40001000,  40001a7f] {      a80} Kern
   no-issue-48u/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
        [ 40002000,  4007afff] {    79000} Kern
   no-issue-48u/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
        [ 40090000,  4009629f] {     62a0} Sigma0 sigma0
        [ 400a0000,  400a6177] {     6178} Sigma0 sigma0
        [ 41000000,  4100f51f] {     f520} Boot   bootstrap
        [ 41100000,  4118efff] {    8f000} Root   Module
        [ 80100000,  80245c73] {   145c74} Root   genode/core
      API Version: (87) experimental
      Sigma0 config    ip:40090100 sp:00000000
      Roottask config  ip:80100000 sp:00000000
      Starting kernel
   no-issue-48u/build/foc_odroid-x2/kernel/fiasco.oc/fiasco at 40001258
   Hello from Startup::stage2
   Per_cpu_data_alloc: (orig: 0xf0068d50-0xf00697d0)
   Number of IRQs available at this GIC: 160
   FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
   p: dbl/sngl
   L2: ID=4100c4c8 Type=1a340340 Aux=7e470001 WMask=ffff S=0
   L2: Type L2C-310 Size = 1024kB  Ways=16 Waysize=64
   Watchdog initialized
   SERIAL ESC: allocated IRQ 85 for serial uart
   Not using serial hack in slow timer handler.
   \0x1b[1;32mWelcome to Fiasco.OC (arm)!
   \0x1b[0;32mL4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden
   Rev: 7aa62e3-dirty compiled with gcc 4.9.2 for Samsung Exynos []
   Build: #3 Thu Jun  4 10:16:23 EDT 2015
   \0x1b[0m
   Per_cpu_data_alloc: (orig: 0xf0068d50-0xf00697d0)
   Allocate 2688 bytes (3KB) for CPU[4] local storage (offset=11872b0,
   0xf11f0000-0xf11f0a80)
   Timer for CPU0 is at IRQ 28
   Number of CPUs: 4
   Calibrating timer loop... Per_cpu_data_alloc: (orig:
   0xf0068d50-0xf00697d0)
   done.
   Allocate 2688 bytes (3KB) for CPU[1] local storage (offset=11892b0,
   0xf11f2000-0xf11f2a80)
   MDB: use page size: 20
   FPU1: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
   p: dbl/sngl
   MDB: use page size: 12
   Timer for CPU1 is at IRQ 28
   Per_cpu_data_alloc: (orig: 0xf0068d50-0xf00697d0)
   SAllocate 2688 bytes (3KB) for CPU[2] local storage (offset=11682b0,
   0xf11d1000-0xf11d1a80)
   ICache config: ON
   GID_PFR[01]:  00001231 00000011M ID_[DA]FR0: 00010444 00000000
   AID_MMFR[04]: 00100103 20000000 01230000 00102111
   0FPU2: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
   p: dbl/sngl
   :CPU[1]: goes to idle loop
     Timer for CPU2 is at IRQ 28
   HCache config: ON
   eID_PFR[01]:  00001231 00000011l ID_[DA]FR0: 00010444 00000000
   lID_MMFR[04]: 00100103 20000000 01230000 00102111
   Per_cpu_data_alloc: (orig: 0xf0068d50-0xf00697d0)
   CPU[2]: goes to idle loop
   oAllocate 2688 bytes (3KB) for CPU[3] local storage (offset=116b2b0,
   0xf11d4000-0xf11d4a80)
   !FPU3: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
   p: dbl/sngl

   Timer for CPU3 is at IRQ 28
     Cache config: ON
     ID_PFR[01]:  00001231 00000011K ID_[DA]FR0: 00010444 00000000
   IID_MMFR[04]: 00100103 20000000 01230000 00102111
   PCPU[3]: goes to idle loop
     @ 40002000
      allocated 4KB for maintenance structures
   SIGMA0: Dump of all resource maps
   RAM:------------------------
   [4:40000000;40000fff]
   [0:4007b000;4008ffff]
   [0:40097000;4009ffff]
   [0:400a7000;410fffff]
   [4:41100000;4118efff]
   [0:4118f000;800fffff]
   [4:80100000;80245fff]
   [0:80246000;bbffffff]
   IOMEM:----------------------
   [0:0;3fffffff]
   [0:bd000000;ffffffff]

   KIP @ 40002000
        magic: 4be6344c
      version: 87024444
             sigma0  esp: 00000000  eip: 40090100
             sigma1  esp: 00000000  eip: 00000000
               root  esp: 00000000  eip: 80100000
   MBI @ 40000000
     mod[3] [41100000,41100110) config
     mod[4] [41101000,41151c30) init
     mod[5] [41152000,4118e514) test-printf
   :ram_alloc: Allocator 80235ed8 dump:
     Block: [4007b000,40090000) size=00015000 avail=00015000
   max_avail=00015000
     Block: [40097000,4009701c) size=0000001c avail=00000000
   max_avail=00015000
     Block: [4009701c,40097038) size=0000001c avail=00000000
   max_avail=00000000
     Block: [40097038,400a0000) size=00008fc8 avail=00008fc8
   max_avail=00008fc8
     Block: [400a7000,400a701c) size=0000001c avail=00000000
   max_avail=3ef71000
     Block: [400a701c,400a7038) size=0000001c avail=00000000
   max_avail=00000000
     Block: [400a7038,41100000) size=01058fc8 avail=01058fc8
   max_avail=01058fc8
     Block: [4118f000,80100000) size=3ef71000 avail=3ef71000
   max_avail=3ef71000
     Block: [80246000,bc000000) size=3bdba000 avail=3bdba000
   max_avail=3bdba000
     => mem_size=2077892608 (1981 MB) / mem_avail=2077892496 (1981 MB)
   :region_alloc: Allocator 80237048 dump:
     Block: [00001000,20000000) size=1ffff000 avail=1ffff000
   max_avail=1ffff000
     Block: [30000000,40000000) size=10000000 avail=10000000
   max_avail=1ffff000
     Block: [40001000,40002000) size=00001000 avail=00001000
   max_avail=1ffff000
     Block: [40003000,4007b000) size=00078000 avail=00078000
   max_avail=00078000
     Block: [40090000,40097000) size=00007000 avail=00007000
   max_avail=1ffff000
     Block: [400a0000,400a7000) size=00007000 avail=00007000
   max_avail=03ff0000
     Block: [bc000000,bfff0000) size=03ff0000 avail=03ff0000
   max_avail=03ff0000
     => mem_size=872898560 (832 MB) / mem_avail=872898560 (832 MB)
   :io_mem: Allocator 80236334 dump:
     Block: [00000000,40000000) size=40000000 avail=40000000
   max_avail=40000000
     Block: [40001000,40002000) size=00001000 avail=00001000
   max_avail=40000000
     Block: [40003000,4007b000) size=00078000 avail=00078000
   max_avail=00078000
     Block: [40090000,40097000) size=00007000 avail=00007000
   max_avail=00078000
     Block: [400a0000,400a7000) size=00007000 avail=00007000
   max_avail=43ffffff
     Block: [bc000000,ffffffff) size=43ffffff avail=43ffffff
   max_avail=43ffffff
     => mem_size=2215145471 (2112 MB) / mem_avail=2215145471 (2112 MB)
   :io_port: Allocator 80236790 dump:
   :irq: Allocator 80236bec dump:
     Block: [00000000,00000260) size=00000260 avail=00000260
   max_avail=00000260
     => mem_size=608 (0 MB) / mem_avail=608 (0 MB)
   :rom_fs: Rom_fs 802378fc dump:
     Rom: [41101000,41151c30) init
     Rom: [41100000,41100110) config
     Rom: [40002000,40003000) l4v2_kip
     Rom: [40002000,40003000) kip
     Rom: [41152000,4118e514) test-printf
   :core ranges: Allocator 8023987c dump:
     Block: [4007b000,40090000) size=00015000 avail=00015000
   max_avail=00015000
     Block: [40097000,400a0000) size=00009000 avail=00009000
   max_avail=7bf59000
     Block: [400a7000,bc000000) size=7bf59000 avail=7bf59000
   max_avail=7bf59000
     => mem_size=2079813632 (1983 MB) / mem_avail=2079813632 (1983 MB)
   \0x1b[32mGenode 15.05-40-gae2eab6\0x1b[0m
   int main(): \0x1b[33m--- create local services ---\0x1b[0m
   int main(): \0x1b[33m--- start init ---\0x1b[0m
   int main(): \0x1b[33mtransferred 1981 MB to init\0x1b[0m
   int main(): \0x1b[33m--- init created, waiting for exit condition
   ---\0x1b[0m
   init] \0x1b[31mCould not open ROM session for module "ld.lib.so"\0x1b[0m
   init -> test-printf] -1 = -1 = -1
   [init] virtual void Genode::Child_policy::exit(int): \0x1b[33mchild
   "test-printf" exited with exit value 0\0x1b[0m

To support Fiasco.OC on Genode we use a patch from Stefan Kalkowski:

   diff --git a/repos/base-foc/lib/mk/l4re_support.mk
   b/repos/base-foc/lib/mk/l4re_support.mk
   index 8058093..108ec4a 100644
   --- a/repos/base-foc/lib/mk/l4re_support.mk
   +++ b/repos/base-foc/lib/mk/l4re_support.mk
   @@ -6,7 +6,7 @@
     ifeq ($(called_from_lib_mk),yes)

     # packages in 'l4/pkg/'
   -PKGS = uclibc-headers uclibc-minimal l4util cxx
   +PKGS = crtn uclibc-headers l4util cxx uclibc-minimal libstdc++-headers

     include $(REP_DIR)/mk/l4_pkg.mk
     all: $(PKG_TAGS)


And this is our patch to support the compilation of Fiasco.OC+Genode for 
Odroid-X2. The patch is not completed, but allows to run the printf 
example. We are based on the Arndale Exynos5 to support the Odroid-X2. 
There are some source code that is specific for the Exynos5 that we must 
change.


Best regards

On 06/04/2015 12:44 AM, sunyu wrote:

Hi,

I have  run 
Fiasco.oc(http://svn.tudos.org/repos/oc/tudos/trunk/l4/,http://os.inf.tu-dresden.de/download/snapshots-oc/)on 
Exynos4412 sucessfully,but i'm not sure what difference between it and 
the fork of Fiasco.OC by Genode.There is the serial output:



------------------------------------------------------------------------------ 


downloading of 935936 bytes finished
Kernel size: 000e4000
Ramdisk size: 00000000
Booting raw image..
Boot with zImage
Wrong Ramdisk Image Format
[err] boot_get_ramdisk

Starting kernel ...


L4 Bootstrapper
  Build: #2 2015��年 06��月 04��日 ��星��期�11:08:19 CST, 4.7.3
  Scanning up to 1024 MB RAM, starting at offset 32MB
  Memory size is 1024MB (40000000 - 7fffffff)
  RAM: 0000000040000000 - 000000007fffffff: 1048576kB
  Total RAM: 1024MB
  Scanning fiasco
  Scanning sigma0
  Scanning moe
  Moving up to 5 modules behind 41100000
  moving module 02 { 410b2000-410e3623 } -> { 411a2000-411d3623 } [202276]
  moving module 01 { 410a8000-410b133b } -> { 41198000-411a133b } [37692]
  moving module 00 { 41044000-410a706b } -> { 41134000-4119706b } [405612]
  moving module 04 { 4102a000-4104357b } -> { 4111a000-4113357b } [103804]
  moving module 03 { 41010000-41029457 } -> { 41100000-41119457 } [103512]
  Loading fiasco
  Loading sigma0
  Loading moe
  find kernel info page...
  found kernel info page at 0x40002000
Regions of list 'regions'
    [ 40000000,  400000e3] {       e4} Root   mbi_rt
    [ 40001000,  40001b7f] {      b80} Kern   fiasco
    [ 40002000,  40072fff] {    71000} Kern   fiasco
    [ 40090000,  400968fb] {     68fc} Sigma0 sigma0
    [ 40098000,  4009e177] {     6178} Sigma0 sigma0
    [ 40140000,  4016e6b3] {    2e6b4} Root   moe
    [ 40170000,  40186f13] {    16f14} Root   moe
    [ 41000000,  4100f4ff] {     f500} Boot   bootstrap
    [ 41100000,  41133fff] {    34000} Root   Module
  API Version: (87) experimental
  Sigma0 config    ip:40090100 sp:00000000
  Roottask config  ip:40140260 sp:00000000
  Starting kernel fiasco at 40001360
Hello from Startup::stage2
Per_cpu_data_alloc: (orig: 0xf005fd10-0xf0060790)
Number of IRQs available at this GIC: 160

FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: 
dbl/sngl

Watchdog initialized
SERIAL ESC: allocated IRQ 85 for serial uart
Not using serial hack in slow timer handler.
Welcome to Fiasco.OC (arm)!
L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden
Rev: unknown compiled with gcc 4.7.3 for Samsung Exynos    []
Build: #1 Thu Jun  4 10:54:54 CST 2015

Per_cpu_data_alloc: (orig: 0xf005fd10-0xf0060790)

KERNEL: Warning: Buddy::alloc: Size mismatch: a80 v 1000

Allocate 2688 bytes (3KB) for CPU[4] local storage (offset=118a2f0, 
0xf11ea000-0xf)

Timer for CPU0 is at IRQ 28
Number of CPUs: 4
11===========interupts=1
Calibrating timer loop... 22===========interupts=1
done.
MDB: use page size: 20
MDB: use page size: 12
SIGMA0: Hello!
  KIP @ 40002000
  allocated 4KB for maintenance structures
SIGMA0: Dump of all resource maps
RAM:------------------------
[4:40000000;40000fff]
[0:40073000;4008ffff]
[0:40097000;40097fff]
[0:4009f000;4013ffff]
[4:40140000;4016efff]
[0:4016f000;4016ffff]
[4:40170000;40186fff]
[0:40187000;410fffff]
[4:41100000;41133fff]
[0:41134000;7effffff]
IOMEM:----------------------
[0:0;3fffffff]
[0:80000000;ffffffff]
MOE: Hello world
MOE: found 1031188 KByte free memory
MOE: found RAM from 40000000 to 7f000000
MOE: allocated 1008 KByte for the page array @0x40187000
MOE: virtual user address space [0-bfffffff]
MOE: rom name space cap -> [C:501000]
  BOOTFS: [41100000-41119458] [C:503000] l4re
  BOOTFS: [4111a000-4113357c] [C:504000] hello
MOE: cmdline: moe --init=rom/hello
MOE: Starting: rom/hello
MOE: loading 'rom/hello'
Hello World!
Hello World!
Hello World!
------------------------------------------------------------------------------------------


I have modified the Fiasco.oc&L4re,all the modifications are as two 
'diff' files shown,and two configuration files are attached.


P.S

    I have tested the modified Fiasco.oc in Genode(15.05) by replacing 
files(Genode/contrib/.../kernel/fiasco,configuration),but there is a 
problem during execution(different from yours),is it caused by wrong 
configuration?

There is the output:
------------------------------------------------------------------------------------------
Starting kernel ...

Hello from Startup::stage2
Per_cpu_data_alloc: (orig: 0xf006b628-0xf006bfe8)
Number of IRQs available at this GIC: 160
Cache config: ON
ID_PFR[01]:  00001231 00000011 ID_[DA]FR0: 00010444 00000000
ID_MMFR[04]: 00100103 20000000 01230000 00102111

FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: 
dbl/sngl

Watchdog initialized
SERIAL ESC: allocated IRQ 305 for serial uart
Not using serial hack in slow timer handler.
Welcome to Fiasco.OC (arm)!
L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden

Rev: rUnversioned director compiled with gcc 4.9.2 for Samsung 
Exynos    []

Build: #1 2015��年 06��月 02��日 ��星��期��二 13:19:19 CST

Per_cpu_data_alloc: (orig: 0xf006b628-0xf006bfe8)

KERNEL: Warning: Buddy::alloc: Size mismatch: 9c0 v 1000

Allocate 2496 bytes (2KB) for CPU[4] local storage (offset=117b9d8, 
0xf11e7000-0xf)

Timer for CPU0 is at IRQ 28
Number of CPUs: 4


KERNEL: Warning: No page-fault handler for 0xee620004, error 0x400808, 
pc f0040700


Best regards
Sunyu






On 2015年06月04日 04:28, Reinier Millo Sánchez wrote:

Hi Sunyu


We are using GenodeOS(15.05) with Fiasco.OC r67 
(http://github.com/skalk/foc.git). We have made all configuration and 
passed the compilation (printf.run) too. To get the raw image we have 
used genode-arm-obj-copy.
In our case the Fiasco.OC don't starts successfully, the execution 
stops at 'Calibrating loop time...'. We have also tested it on the 
Fiasco.OC snapshot and got the same problem. There is the serial 
output using Genode:


    Boot with zImage
    Starting kernel ...
    L4 Bootstrapper
      Build: #2 Mon Jun  1 13:06:39 EDT 2015, 4.7.4
      Scanning up to 2047 MB RAM
      Memory size is 2047MB (40000000 - bfefffff)
      RAM: 0000000040000000 - 00000000bfefffff: 2096128kB
      Total RAM: 2047MB
      mod05: 41153000-4118b960: genode/test-printf
      mod04: 41104000-41152908: genode/init
      mod03: 41103000-41103110: genode/config
      mod02: 41089000-411021c8: genode/core
      mod01: 4107f000-41088374: sigma0
      mod00: 41015000-4107e8ac:
    /home/alexy/workOS/genodeos/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
      Moving up to 6 modules behind 41100000
      moving module 00 { 41015000-4107e8ab } -> { 41277000-412e08ab }
    [432300]
      moving module 01 { 4107f000-41088373 } -> { 412e1000-412ea373 }
    [37748]
      moving module 02 { 41089000-411021c7 } -> { 412eb000-413641c7 }
    [496072]
      moving module 03 { 41103000-4110310f } -> { 41100000-4110010f }
    [272]
      moving module 04 { 41104000-41152907 } -> { 41101000-4114f907 }
    [321800]
      moving module 05 { 41153000-4118b95f } -> { 41150000-4118895f }
    [231776]
      Scanning
    /home/alexy/workOS/genodeos/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
    -serial_esc
      Scanning sigma0
      Scanning genode/core
      Relocated mbi to [0x4100e000-0x4100e14d]
      Loading kOS/genodeos/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
      Loading sigma0
      Loading genode/core
      find kernel info page...
      found kernel info page at 0x40002000
    Regions of list 'regions'
        [ 40001000,  40001bff] {      c00} Kern
    kOS/genodeos/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
        [ 40002000,  40076fff] {    75000} Kern
    kOS/genodeos/build/foc_odroid-x2/kernel/fiasco.oc/fiasco
        [ 400a0000,  400a673b] {     673c} Sigma0 sigma0
        [ 400a8000,  400ae17b] {     617c} Sigma0 sigma0
        [ 41000000,  410143f7] {    143f8} Boot   bootstrap
        [ 4100e000,  4100e24a] {      24b} Root   Multiboot info
        [ 41100000,  4118895f] {    88960} Root   Module
        [ 80100000,  8025271f] {   152720} Root   genode/core
      API Version: (87) experimental
      Sigma0 config    ip:400a0100 sp:41013de4
      Roottask config  ip:80100000 sp:00000000
      Starting kernel
    kOS/genodeos/build/foc_odroid-x2/kernel/fiasco.oc/fiasco at 400013c0
    Hello from Startup::stage2
    Per_cpu_data_alloc: (orig: 0xf0066658-0xf00670a8)
    Number of IRQs available at this GIC: 160
    Cache config: ON
    ID_PFR[01]:  00001231 00000011 ID_[DA]FR0: 00010444 00000000
    ID_MMFR[04]: 00100103 20000000 01230000 00102111
    FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t:
    hard, p: dbl/sngl
    L2: ID=4100c4c8 Type=1a340340 Aux=7e470001 WMask=ffff S=0
    L2: Type L2C-310 Size = 1024kB
    Watchdog initialized
    SERIAL ESC: allocated IRQ 85 for serial uart
    Not using serial hack in slow timer handler.
    Welcome to Fiasco.OC (arm)!
    L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden
    Rev: 95b378f compiled with gcc 4.7.4 for Samsung Exynos    []
    Build: #1 Mon Jun  1 13:06:23 EDT 2015
    
    Per_cpu_data_alloc: (orig: 0xf0066658-0xf00670a8)
    Allocate 2640 bytes (3KB) for CPU[4] local storage
    (offset=117f9a8, 0xf11e6000-0xf11e6a50)
    Timer for CPU0 is at IRQ 28
    Number of CPUs: 4
    Calibrating timer loop... Per_cpu_data_alloc: (orig:
    0xf0066658-0xf00670a8)
    Allocate 2640 bytes (3KB) for CPU[1] local storage
    (offset=11809a8, 0xf11e7000-0xf11e7a50)
    Cache config: ON
    ID_PFR[01]:  00001231 00000011 ID_[DA]FR0: 00010444 00000000
    ID_MMFR[04]: 00100103 20000000 01230000 00102111
    FPU1: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t:
    hard, p: dbl/sngl
    Per_cpu_data_alloc: (orig: 0xf0066658-0xf00670a8)
    Timer for CPU1 is at IRQ 28
    Allocate 2640 bytes (3KB) for CPU[2] local storage
    (offset=118c9a8, 0xf11f3000-0xf11f3a50)
    CPU[1]: goes to idle loop
    Cache config: ON
    ID_PFR[01]:  00001231 00000011 ID_[DA]FR0: 00010444 00000000
    ID_MMFR[04]: 00100103 20000000 01230000 00102111
    FPU2: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t:
    hard, p: dbl/sngl
    Per_cpu_data_alloc: (orig: 0xf0066658-0xf00670a8)
    Timer for CPU2 is at IRQ 28
    Allocate 2640 bytes (3KB) for CPU[3] local storage
    (offset=118f9a8, 0xf11f6000-0xf11f6a50)
    CPU[2]: goes to idle loop
    Cache config: ON
    ID_PFR[01]:  00001231 00000011 ID_[DA]FR0: 00010444 00000000
    ID_MMFR[04]: 00100103 20000000 01230000 00102111
    FPU3: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t:
    hard, p: dbl/sngl
    Timer for CPU3 is at IRQ 28
    CPU[3]: goes to idle loop
    \00\FF\00OK


I have attached the configuration that we are using to compile the 
Fiasco.OC + L4re with Genode. Can you share the configuration that 
have used to compile Fiasco.OC? and what repository are you using?


Best regards

On 05/30/2015 02:57 AM, 四枚羽根 wrote:

Hi,

We have alreadly got fiasco.oc(R67) running on the Exynos4412 
successfully,
and tested Genode(13.05) on pandaboard.So i am trying to test 
Genode(13.05）

with fiasco.oc(R67) on Exynos4412.

Have made all the configuration and passed the 
compilation(printf.run),i get a 'image.elf' and then change it to 
'image.raw'.
The Fiasco.oc starts successfully during the execution of image.raw 
on Exynos4412,but end with the error,i know it is about protection 
domain.
Do you have any idea about the error? Then can you show me the log 
of your Fiasco.oc's boot(on Odroid-X2).


Thanks and regards
Sunyu

发自 Windows 邮件



--
Lic. Reinier Millo Sánchez
Centro de Estudios de Informática
Universidad Central "Marta Abreu" de Las Villas
Carretera a Camajuaní Km 5 1/2
Santa Clara, Villa Clara, Cuba
CP 54830

"antes de discutir ... respira;
   antes de hablar ... escucha;
  antes de escribir ... piensa;
   antes de herir ... siente;
  antes de rendirte ... intenta;
   antes de morir ... vive"




--
Lic. Reinier Millo Sánchez
Centro de Estudios de Informática
Universidad Central "Marta Abreu" de Las Villas
Carretera a Camajuaní Km 5 1/2
Santa Clara, Villa Clara, Cuba
CP 54830

"antes de discutir ... respira;
  antes de hablar ... escucha;
 antes de escribir ... piensa;
  antes de herir ... siente;
 antes de rendirte ... intenta;
  antes de morir ... vive"


diff --git a/repos/base-foc/config/odroid-x2.kernel b/repos/base-foc/config/odroid-x2.kernel
new file mode 100644
index 0000000..d7b675f
--- /dev/null
+++ b/repos/base-foc/config/odroid-x2.kernel
@@ -0,0 +1,103 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Fiasco configuration
+#
+
+#
+# Target configuration
+#
+# CONFIG_IA32 is not set
+# CONFIG_AMD64 is not set
+CONFIG_ARM=y
+# CONFIG_PF_S3C2410 is not set
+# CONFIG_PF_REALVIEW is not set
+# CONFIG_PF_ZYNQ is not set
+# CONFIG_PF_OMAP is not set
+CONFIG_PF_EXYNOS=y
+# CONFIG_PF_SUNXI is not set
+# CONFIG_PF_IMX is not set
+# CONFIG_PF_INTEGRATOR is not set
+# CONFIG_PF_XSCALE is not set
+# CONFIG_PF_SA1100 is not set
+# CONFIG_PF_TEGRA is not set
+# CONFIG_PF_BCM2835 is not set
+# CONFIG_PF_KIRKWOOD is not set
+CONFIG_BSP_NAME="exynos"
+CONFIG_PF_EXYNOS4=y
+CONFIG_CPU_SUSPEND=y
+CONFIG_PF_EXYNOS_PKG_IDS=""
+# CONFIG_PF_EXYNOS4_4210 is not set
+CONFIG_PF_EXYNOS4_4412=y
+# CONFIG_PF_EXYNOS5_5250 is not set
+# CONFIG_PF_EXYNOS5_5410 is not set
+CONFIG_PF_EXYNOS_UART_NATIVE=y
+CONFIG_PF_EXYNOS_UART_NR=1
+CONFIG_PF_EXYNOS_TIMER_MCT=y
+# CONFIG_PF_EXYNOS_TIMER_MP is not set
+# CONFIG_PF_EXYNOS_TIMER_PWM is not set
+CONFIG_PF_EXYNOS_EXTGIC=y
+CONFIG_ABI_VF=y
+CONFIG_PF_ARM_MP_CAPABLE=y
+CONFIG_CAN_ARM_CPU_CORTEX_A9=y
+CONFIG_CAN_ARM_CACHE_L2CXX0=y
+CONFIG_ARM_CORTEX_A9=y
+# CONFIG_ARM_ALIGNMENT_CHECK is not set
+# CONFIG_ARM_EM_STD is not set
+CONFIG_ARM_EM_NS=y
+# CONFIG_ARM_EM_TZ is not set
+# CONFIG_ARM_SECMONIF_NONE is not set
+CONFIG_ARM_SECMONIF_MC=y
+# CONFIG_ARM_SECMONIF_TL is not set
+# CONFIG_ARM_ENABLE_SWP is not set
+CONFIG_ARM_CACHE_L2CXX0=y
+CONFIG_FPU=y
+# CONFIG_ARM_CPU_ERRATA is not set
+
+#
+# Kernel options
+#
+CONFIG_MP=y
+CONFIG_MP_MAX_CPUS=4
+# CONFIG_CONTEXT_8K is not set
+CONFIG_CONTEXT_4K=y
+# CONFIG_FINE_GRAINED_CPUTIME is not set
+CONFIG_SCHED_FIXED_PRIO=y
+CONFIG_VIRT_OBJ_SPACE=y
+
+#
+# Debugging
+#
+CONFIG_INLINE=y
+# CONFIG_NDEBUG is not set
+CONFIG_NO_FRAME_PTR=y
+# CONFIG_STACK_DEPTH is not set
+# CONFIG_LIST_ALLOC_SANITY is not set
+CONFIG_SERIAL=y
+CONFIG_JDB=y
+# CONFIG_JDB_LOGGING is not set
+# CONFIG_JDB_DISASM is not set
+# CONFIG_JDB_GZIP is not set
+# CONFIG_JDB_ACCOUNTING is not set
+# CONFIG_VMEM_ALLOC_TEST is not set
+# CONFIG_DEBUG_KERNEL_PAGE_FAULTS is not set
+# CONFIG_WARN_NONE is not set
+CONFIG_WARN_WARNING=y
+# CONFIG_WARN_ANY is not set
+
+#
+# Compiling
+#
+CONFIG_CC="gcc"
+CONFIG_CXX="g++"
+CONFIG_HOST_CC="gcc"
+CONFIG_HOST_CXX="g++"
+# CONFIG_MAINTAINER_MODE is not set
+CONFIG_LABEL=""
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_PERF_CNT=y
+CONFIG_BIT32=y
+CONFIG_ARM_V7=y
+CONFIG_ARM_V6PLUS=y
+CONFIG_WARN_LEVEL=1
+CONFIG_XARCH="arm"
+CONFIG_ABI="vf"
diff --git a/repos/base-foc/config/odroid-x2.user b/repos/base-foc/config/odroid-x2.user
new file mode 100644
index 0000000..d4e7cd7
--- /dev/null
+++ b/repos/base-foc/config/odroid-x2.user
@@ -0,0 +1,75 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# L4Re Configuration
+#
+# CONFIG_BUILD_ARCH_x86 is not set
+# CONFIG_BUILD_ARCH_amd64 is not set
+CONFIG_BUILD_ARCH_arm=y
+# CONFIG_BUILD_ARCH_ppc32 is not set
+# CONFIG_BUILD_ARCH_sparc is not set
+CONFIG_BUILD_ARCH="arm"
+CONFIG_BUILD_ABI_l4f=y
+CONFIG_BUILD_ABI="l4f"
+CONFIG_CPU="armv7a"
+# CONFIG_CPU_ARM_ARMV4 is not set
+# CONFIG_CPU_ARM_ARMV4T is not set
+# CONFIG_CPU_ARM_ARMV5 is not set
+# CONFIG_CPU_ARM_ARMV5T is not set
+# CONFIG_CPU_ARM_ARMV5TE is not set
+# CONFIG_CPU_ARM_ARMV6 is not set
+# CONFIG_CPU_ARM_ARMV6T2 is not set
+# CONFIG_CPU_ARM_ARMV6ZK is not set
+CONFIG_CPU_ARM_ARMV7A=y
+# CONFIG_CPU_ARM_ARMV7R is not set
+CONFIG_CPU_ARMV6KPLUS=y
+CONFIG_CPU_ARMV6PLUS=y
+CONFIG_PLATFORM_TYPE_exynos4=y
+# CONFIG_PLATFORM_TYPE_imx6 is not set
+# CONFIG_PLATFORM_TYPE_zedboard is not set
+# CONFIG_PLATFORM_TYPE_imx35 is not set
+# CONFIG_PLATFORM_TYPE_rv_pbx is not set
+# CONFIG_PLATFORM_TYPE_exynos5 is not set
+# CONFIG_PLATFORM_TYPE_rv is not set
+# CONFIG_PLATFORM_TYPE_kirkwood is not set
+# CONFIG_PLATFORM_TYPE_pandaboard is not set
+# CONFIG_PLATFORM_TYPE_tegra3 is not set
+# CONFIG_PLATFORM_TYPE_tegra2 is not set
+# CONFIG_PLATFORM_TYPE_cubieboard2 is not set
+# CONFIG_PLATFORM_TYPE_omap3_am33xx is not set
+# CONFIG_PLATFORM_TYPE_parallella is not set
+# CONFIG_PLATFORM_TYPE_rpi_b is not set
+# CONFIG_PLATFORM_TYPE_rv_vexpress_a15 is not set
+# CONFIG_PLATFORM_TYPE_imx51 is not set
+# CONFIG_PLATFORM_TYPE_omap3evm is not set
+# CONFIG_PLATFORM_TYPE_beagleboard is not set
+# CONFIG_PLATFORM_TYPE_imx21 is not set
+# CONFIG_PLATFORM_TYPE_omap5 is not set
+# CONFIG_PLATFORM_TYPE_rv_vexpress is not set
+# CONFIG_PLATFORM_TYPE_rpi_a is not set
+# CONFIG_PLATFORM_TYPE_integrator is not set
+# CONFIG_PLATFORM_TYPE_custom is not set
+CONFIG_PLATFORM_TYPE="exynos4"
+# CONFIG_USE_DROPS_STDDIR is not set
+# CONFIG_USE_DICE is not set
+CONFIG_DROPS_STDDIR="/path/to/l4re"
+CONFIG_DROPS_INSTDIR="/path/to/l4re"
+CONFIG_BID_COLORED_PHASES=y
+
+#
+# Building
+#
+CONFIG_YACC="yacc"
+CONFIG_LEX="flex"
+CONFIG_CTAGS="ctags"
+CONFIG_ETAGS="etags"
+CONFIG_HAVE_LDSO=y
+CONFIG_INT_CPP_NAME_SWITCH=y
+CONFIG_INT_LD_NAME_SWITCH=y
+# CONFIG_BID_STRIP_PROGS is not set
+# CONFIG_BID_GCC_OMIT_FP is not set
+CONFIG_BID_GCC_ENABLE_STACK_PROTECTOR=y
+# CONFIG_BID_GCC_STACK_PROTECTOR_ALL is not set
+CONFIG_BID_GCC_STACK_PROTECTOR=y
+# CONFIG_BID_BUILD_DOC is not set
+# CONFIG_RELEASE_MODE is not set
+CONFIG_MAKECONFS_ADD=""
diff --git a/repos/base-foc/lib/mk/platform_odroid-x2/platform.mk b/repos/base-foc/lib/mk/platform_odroid-x2/platform.mk
new file mode 100644
index 0000000..b3b16c3
--- /dev/null
+++ b/repos/base-foc/lib/mk/platform_odroid-x2/platform.mk
@@ -0,0 +1,6 @@
+#
+# Configuration for L4 build system (for kernel-bindings, sigma0, bootstrap).
+#
+L4_CONFIG = $(call select_from_repositories,config/odroid-x2.user)
+
+include $(REP_DIR)/lib/mk/arm/platform.inc
diff --git a/repos/base-foc/mk/spec-foc_odroid-x2.mk b/repos/base-foc/mk/spec-foc_odroid-x2.mk
new file mode 100644
index 0000000..5a3531e
--- /dev/null
+++ b/repos/base-foc/mk/spec-foc_odroid-x2.mk
@@ -0,0 +1,4 @@
+SPECS += foc_arm platform_odroid-x2
+
+include $(call select_from_repositories,mk/spec-platform_odroid-x2.mk)
+include $(call select_from_repositories,mk/spec-foc_arm.mk)
diff --git a/repos/base-foc/src/core/odroid-x2/target.mk b/repos/base-foc/src/core/odroid-x2/target.mk
new file mode 100644
index 0000000..eed04a1
--- /dev/null
+++ b/repos/base-foc/src/core/odroid-x2/target.mk
@@ -0,0 +1,9 @@
+include $(PRG_DIR)/../target.inc
+
+LD_TEXT_ADDR = 0x80100000
+
+REQUIRES += arm foc_odroid-x2
+SRC_CC   += arm/platform_arm.cc
+INC_DIR  += $(REP_DIR)/src/core/include/arm
+
+vpath platform_services.cc $(GEN_CORE_DIR)
diff --git a/repos/base-foc/src/kernel/odroid-x2/target.mk b/repos/base-foc/src/kernel/odroid-x2/target.mk
new file mode 100644
index 0000000..22f7472
--- /dev/null
+++ b/repos/base-foc/src/kernel/odroid-x2/target.mk
@@ -0,0 +1,5 @@
+REQUIRES       = platform_odroid-x2
+FIASCO_DIR    := $(call select_from_ports,foc)/src/kernel/foc/kernel/fiasco
+KERNEL_CONFIG  = $(REP_DIR)/config/odroid-x2.kernel
+
+-include $(PRG_DIR)/../target.inc
diff --git a/repos/base/include/platform/odroid-x2/drivers/board_base.h b/repos/base/include/platform/odroid-x2/drivers/board_base.h
new file mode 100644
index 0000000..90b610e
--- /dev/null
+++ b/repos/base/include/platform/odroid-x2/drivers/board_base.h
@@ -0,0 +1,55 @@
+/*
+ * \brief  Driver base for Odroid-x2 board
+ * \author Alexy Gallardo Segura
+ * \author Humberto López León
+ * \author Reinier Millo Sánchez <rmi...@uclv.cu>
+ * \date   2015-04-27
+ */
+
+/*
+ * Copyright (C) 2013 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
+#define _INCLUDE__DRIVERS__BOARD_BASE_H_
+
+/* Genode includes */
+#include <platform_exynos4/board_base.h>
+
+namespace Genode { struct Board_base; }
+
+
+/**
+ * Board driver base
+ */
+struct Genode::Board_base : Exynos4
+{
+	enum
+	{
+		/* clock management unit */
+		CMU_MMIO_BASE = 0x10034000,
+		CMU_MMIO_SIZE = 0x18000,
+
+		/* power management unit */
+		PMU_MMIO_BASE = 0x10020000,
+		PMU_MMIO_SIZE = 0x5000, // TODO Check the region size
+
+		/* UART */
+		UART_1_MMIO_BASE = 0x13810000,
+		UART_1_IRQ       = 85,
+		UART_1_CLOCK     = 100000000, // TODO Check SCLK_UART1
+
+		UART_2_MMIO_BASE = 0x13820000,
+		UART_2_IRQ       = 86,
+		UART_2_CLOCK     = 100000000, // TODO Check SCLK_UART2
+
+
+		/* wether board provides security extension */
+		SECURITY_EXTENSION = 0, // TODO Check this value
+	};
+};
+
+#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */
diff --git a/repos/base/include/platform_exynos4/board_base.h b/repos/base/include/platform_exynos4/board_base.h
new file mode 100644
index 0000000..5c26f34
--- /dev/null
+++ b/repos/base/include/platform_exynos4/board_base.h
@@ -0,0 +1,66 @@
+/*
+ * \brief  Board-driver base
+ * \author Alexy Gallardo Segura
+ * \author Humberto López León
+ * \author Reinier Millo Sánchez <rmi...@uclv.cu>
+ * \date   2015-04-28
+ */
+
+/*
+ * Copyright (C) 2013 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _EXYNOS4__BOARD_BASE_H_
+#define _EXYNOS4__BOARD_BASE_H_
+
+namespace Genode { struct Exynos4; }
+
+
+/**
+ * Board-driver base
+ */
+struct Genode::Exynos4
+{
+	enum {
+		/* normal RAM */
+		RAM_0_BASE = 0x40000000,
+		RAM_0_SIZE = 0x60000000,
+
+		/* device IO memory */
+		MMIO_0_BASE = 0x10000000,
+		MMIO_0_SIZE = 0x040000000,
+
+		/* interrupt controller */
+		IRQ_CONTROLLER_BASE         = 0x10480000,
+		IRQ_CONTROLLER_SIZE         = 0x00010000,
+		
+		/* pulse-width-modulation timer  */
+		PWM_MMIO_BASE = 0x139D0000,
+		PWM_MMIO_SIZE = 0x1000, // TODO Check the region size
+		PWM_CLOCK     = 66000000, // TODO Check clock frequency
+		PWM_IRQ_0     = 69,
+
+		/* multicore timer */
+		MCT_MMIO_BASE = 0x10050000,
+		MCT_MMIO_SIZE = 0x1000,
+		// TODO Check the clock value
+		MCT_CLOCK     = 100000000,
+		// TODO Check - L0 & L1 are conected to IRQ combiner
+		MCT_IRQ_L0    = 74,
+		MCT_IRQ_L1    = 80,
+
+		/* CPU cache */
+		CACHE_LINE_SIZE_LOG2 = 6, // TODO Check this value
+
+		/* IRAM */
+		IRAM_BASE = 0x02020000,
+
+		/* hardware name of the primary processor */
+		PRIMARY_MPIDR_AFF_0 = 0,
+	};
+};
+
+#endif /* _EXYNOS4__BOARD_BASE_H_ */
diff --git a/repos/base/mk/spec-platform_odroid-x2.mk b/repos/base/mk/spec-platform_odroid-x2.mk
new file mode 100644
index 0000000..5537b07
--- /dev/null
+++ b/repos/base/mk/spec-platform_odroid-x2.mk
@@ -0,0 +1,17 @@
+#
+# \brief  Build-system configurations for Odrod-x2
+# \author Alexy Gallardo Segura
+# \author Humberto López León
+# \author Reinier Millo Sánchez <rmi...@uclv.cu>
+# \date   2015-04-28
+#
+
+# denote specs that are fullfilled by this spec
+SPECS +=  exynos4 cortex_a9
+
+# add repository relative paths
+REP_INC_DIR += include/platform/odroid-x2
+REP_INC_DIR += include/platform/exynos4
+
+# include implied specs
+include $(call select_from_repositories,mk/spec-cortex_a9.mk)
diff --git a/repos/os/src/drivers/platform/odroid-x2/cmu.h b/repos/os/src/drivers/platform/odroid-x2/cmu.h
new file mode 100644
index 0000000..26d3745
--- /dev/null
+++ b/repos/os/src/drivers/platform/odroid-x2/cmu.h
@@ -0,0 +1,487 @@
+/*
+ * \brief  Regulator driver for clock management unit of Exynos4412 SoC
+ * \author Alexy Gallardo Segura <al...@uclv.cu>
+ * \author Humberto Lopez Leon <humbe...@uclv.cu>
+ * \author Reinier Millo Sanchez <rmi...@uclv.cu>
+ * \date   2015-04-30
+ */
+
+/*
+ * Copyright (C) 2013 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _CMU_H_
+#define _CMU_H_
+
+#include <regulator/consts.h>
+#include <regulator/driver.h>
+#include <drivers/board_base.h>
+#include <os/attached_mmio.h>
+
+using namespace Regulator;
+
+
+class Cmu : public Regulator::Driver,
+            public Genode::Attached_mmio
+{
+	private:
+
+		static const Genode::uint16_t m_values[]; /* M values for frequencies */
+		static const Genode::uint8_t  p_values[]; /* P values for frequencies */
+		static const Genode::uint8_t  s_values[]; /* S values for frequencies */
+
+		template <unsigned OFF>
+		struct Pll_lock : Register<OFF, 32>
+		{
+			struct Pll_locktime : Register<OFF, 32>::template Bitfield<0, 20> { };
+
+			static Genode::uint32_t max_lock_time(Genode::uint8_t pdiv) {
+				return pdiv * 250; };
+		};
+
+		template <unsigned OFF>
+		struct Pll_con0 : Register<OFF, 32>
+		{
+			struct S      : Register<OFF, 32>::template Bitfield < 0,  3> { };
+			struct P      : Register<OFF, 32>::template Bitfield < 8,  6> { };
+			struct M      : Register<OFF, 32>::template Bitfield <16, 10> { };
+			struct Locked : Register<OFF, 32>::template Bitfield <29,  1> { };
+			struct Enable : Register<OFF, 32>::template Bitfield <31,  1> { };
+		};
+
+
+		/***********************
+		 ** CMU CPU registers **
+		 ***********************/
+
+		typedef Pll_lock<0>     Apll_lock;
+		typedef Pll_con0<0x100> Apll_con0;
+
+		struct Clk_src_cpu : Register<0x200, 32>
+		{
+			struct Mux_cpu_sel : Bitfield<16, 1>
+			{
+				enum { MOUT_APLL, SCLK_MPLL};
+			};
+		};
+
+		struct Clk_mux_stat_cpu : Register<0x400, 32>
+		{
+			struct Cpu_sel : Bitfield<16, 3>
+			{
+				enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
+			};
+		};
+
+		struct Clk_div_cpu0 : Register<0x500, 32>
+		{
+			/* Cpu0 divider values for frequencies 200 - 1700 */
+			static const Genode::uint32_t values[];
+		};
+
+		struct Clk_div_cpu1 : Register<0x504, 32>
+		{
+			/* Divider for cpu1 doesn't change */
+			enum { FIX_VALUE = 32 };
+		};
+
+		struct Clk_div_stat_cpu0 : Register<0x600, 32>
+		{
+			struct Div_arm      : Bitfield< 0, 1> {};
+			struct Div_cpud     : Bitfield< 4, 1> {};
+			struct Div_acp      : Bitfield< 8, 1> {};
+			struct Div_pheriph  : Bitfield<12, 1> {};
+			struct Div_atb      : Bitfield<16, 1> {};
+			struct Div_pclk_dbg : Bitfield<20, 1> {};
+			struct Div_apll     : Bitfield<24, 1> {};
+			struct Div_arm2     : Bitfield<28, 1> {};
+
+			static bool in_progress(access_t stat_word)
+			{
+				return stat_word & (Div_arm::bits(1)      |
+				                    Div_cpud::bits(1)     |
+				                    Div_acp::bits(1)      |
+				                    Div_pheriph::bits(1)  |
+				                    Div_atb::bits(1)      |
+				                    Div_pclk_dbg::bits(1) |
+				                    Div_apll::bits(1)     |
+				                    Div_arm2::bits(1));
+			}
+		};
+
+		struct Clk_div_stat_cpu1 : Register<0x604, 32>
+		{
+			struct Div_copy : Bitfield<0, 1> { };
+			struct Div_hpm  : Bitfield<4, 1> { };
+
+			static bool in_progress(access_t stat_word)
+			{
+				return stat_word & (Div_copy::bits(1) |
+				                    Div_hpm::bits(1));
+			}
+		};
+
+
+		/************************
+		 ** CMU CORE registers **
+		 ************************/
+
+		typedef Pll_lock<0x4000> Mpll_lock;
+		typedef Pll_con0<0x4100> Mpll_con0;
+
+		struct Clk_src_core1 : Register<0x4204, 32>
+		{
+			struct Mux_mpll_sel : Bitfield<8, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
+		};
+
+		struct Clk_gate_ip_acp   : Register<0x8800, 32> { };
+		struct Clk_gate_ip_isp0  : Register<0xc800, 32> { };
+		struct Clk_gate_ip_isp1  : Register<0xc804, 32> { };
+		struct Clk_gate_sclk_isp : Register<0xc900, 32> { };
+
+
+		/***********************
+		 ** CMU TOP registers **
+		 ***********************/
+
+		typedef Pll_lock<0x10020> Cpll_lock;
+		typedef Pll_lock<0x10030> Epll_lock;
+		typedef Pll_lock<0x10040> Vpll_lock;
+		typedef Pll_lock<0x10050> Gpll_lock;
+		typedef Pll_con0<0x10120> Cpll_con0;
+		typedef Pll_con0<0x10130> Epll_con0;
+		typedef Pll_con0<0x10140> Vpll_con0;
+		typedef Pll_con0<0x10150> Gpll_con0;
+
+		struct Clk_src_top2 : Register<0x10218, 32>
+		{
+			struct Mux_mpll_user_sel : Bitfield<20, 1> { enum { XXTI, MOUT_MPLL}; };
+		};
+
+		struct Clk_src_fsys : Register<0x10244, 32>
+		{
+			struct Sata_sel     : Bitfield<24, 1> {
+				enum { SCLK_MPLL_USER, SCLK_BPLL_USER }; };
+			struct Usbdrd30_sel : Bitfield<28, 1> {
+				enum { SCLK_MPLL_USER, SCLK_CPLL }; };
+		};
+
+		struct Clk_src_mask_fsys : Register<0x10340, 32>
+		{
+			struct Mmc0_mask     : Bitfield<0,  1> { enum { MASK, UNMASK }; };
+			struct Sata_mask     : Bitfield<24, 1> { enum { MASK, UNMASK }; };
+			struct Usbdrd30_mask : Bitfield<28, 1> { enum { MASK, UNMASK }; };
+		};
+
+		struct Clk_div_fsys0 : Register<0x10548, 32>
+		{
+			struct Sata_ratio     : Bitfield<20, 4> { };
+			struct Usbdrd30_ratio : Bitfield<24, 4> { };
+		};
+
+		struct Clk_div_stat_fsys0 : Register<0x10648, 32>
+		{
+			struct Div_sata     : Bitfield<20, 1> {};
+			struct Div_usbdrd30 : Bitfield<24, 1> {};
+		};
+
+		struct Clk_gate_ip_gscl  : Register<0x10920, 32> { };
+		struct Clk_gate_ip_disp1 : Register<0x10928, 32>
+		{
+			struct Clk_mixer     : Bitfield<5, 1> { };
+			struct Clk_hdmi      : Bitfield<6, 1> { };
+		};
+		struct Clk_gate_ip_mfc   : Register<0x1092c, 32> { };
+		struct Clk_gate_ip_g3d   : Register<0x10930, 32> { };
+		struct Clk_gate_ip_gen   : Register<0x10934, 32> { };
+
+		struct Clk_gate_ip_fsys : Register<0x10944, 32>
+		{
+			struct Pdma0         : Bitfield<1,  1> { };
+			struct Pdma1         : Bitfield<2,  1> { };
+			struct Sdmmc0        : Bitfield<12, 1> { };
+			struct Usbhost20     : Bitfield<18, 1> { };
+
+		};
+
+		struct Clk_src_disp1_0 : Register<0x1022c, 32>
+		{
+			struct Hdmi_sel : Bitfield<20, 1> { };
+		};
+
+		struct Clk_src_mask_disp1_0 : Register<0x1032c, 32>
+		{
+			struct Hdmi_mask : Bitfield<20, 1> { };
+		};
+
+		struct Clk_gate_ip_peric : Register<0x10950, 32>
+		{
+			struct Clk_uart2   : Bitfield<2,  1> { };
+			struct Clk_i2chdmi : Bitfield<14, 1> { };
+			struct Clk_pwm     : Bitfield<24, 1> { };
+		};
+
+		struct Clk_gate_block : Register<0x10980, 32>
+		{
+			struct Clk_disp1 : Bitfield<5, 1> { };
+			struct Clk_gen   : Bitfield<2, 1> { };
+		};
+
+
+		/*************************
+		 ** CMU CDREX registers **
+		 *************************/
+
+		typedef Pll_lock<0x20010> Bpll_lock;
+		typedef Pll_con0<0x20110> Bpll_con0;
+
+		struct Pll_div2_sel : Register<0x20a24, 32>
+		{
+			struct Mpll_fout_sel : Bitfield<4, 1> {
+				enum { MPLL_FOUT_HALF, MPLL_FOUT }; };
+		};
+
+
+		/*******************
+		 ** CPU functions **
+		 *******************/
+
+		Cpu_clock_freq _cpu_freq;
+
+		void _cpu_clk_freq(unsigned long level)
+		{
+			unsigned freq;
+			switch (level) {
+			case CPU_FREQ_200:
+				freq = 0;
+				break;
+			case CPU_FREQ_400:
+				freq = 1;
+				break;
+			case CPU_FREQ_600:
+				freq = 2;
+				break;
+			case CPU_FREQ_800:
+				freq = 3;
+				break;
+			case CPU_FREQ_1000:
+				freq = 4;
+				break;
+			case CPU_FREQ_1200:
+				freq = 5;
+				break;
+			case CPU_FREQ_1400:
+				freq = 6;
+				break;
+			case CPU_FREQ_1600:
+				freq = 7;
+				break;
+			case CPU_FREQ_1700:
+				freq = 8;
+				break;
+			default:
+				PWRN("Unsupported CPU frequency level %ld", level);
+				PWRN("Supported values are 200, 400, 600, 800 MHz");
+				PWRN("and 1, 1.2, 1.4, 1.6, 1.7 GHz");
+				return;
+			};
+
+			/**
+			 * change clock divider values
+			 */
+
+			/* cpu0 divider */
+			write<Clk_div_cpu0>(Clk_div_cpu0::values[freq]);
+			while (Clk_div_stat_cpu0::in_progress(read<Clk_div_stat_cpu0>())) ;
+
+			/* cpu1 divider */
+			write<Clk_div_cpu1>(Clk_div_cpu1::FIX_VALUE);
+			while (Clk_div_stat_cpu1::in_progress(read<Clk_div_stat_cpu1>())) ;
+
+
+			/**
+			 * change APLL frequency
+			 */
+
+			/* change reference clock to MPLL */
+			write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::SCLK_MPLL);
+			while (read<Clk_mux_stat_cpu::Cpu_sel>()
+			       != Clk_mux_stat_cpu::Cpu_sel::SCLK_MPLL) ;
+
+			/* set lock time */
+			unsigned pdiv = p_values[freq];
+			write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
+
+			/* change P, M, S values of APLL */
+			write<Apll_con0::P>(p_values[freq]);
+			write<Apll_con0::M>(m_values[freq]);
+			write<Apll_con0::S>(s_values[freq]);
+
+			while (!read<Apll_con0::Locked>()) ;
+
+			/* change reference clock back to APLL */
+			write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::MOUT_APLL);
+			while (read<Clk_mux_stat_cpu::Cpu_sel>()
+			       != Clk_mux_stat_cpu::Cpu_sel::MOUT_APLL) ;
+
+			_cpu_freq = static_cast<Cpu_clock_freq>(level);
+		}
+
+
+		/**********************
+		 ** Device functions **
+		 **********************/
+
+		void _hdmi_enable()
+		{
+			write<Clk_gate_ip_peric::Clk_i2chdmi>(1);
+			Clk_gate_ip_disp1::access_t gd1 = read<Clk_gate_ip_disp1>();
+			Clk_gate_ip_disp1::Clk_mixer::set(gd1, 1);
+			Clk_gate_ip_disp1::Clk_hdmi::set(gd1, 1);
+			write<Clk_gate_ip_disp1>(gd1);
+			write<Clk_gate_block::Clk_disp1>(1);
+			write<Clk_src_mask_disp1_0::Hdmi_mask>(1);
+			write<Clk_src_disp1_0::Hdmi_sel>(1);
+		}
+
+
+
+
+
+		void _enable(Regulator_id id)
+		{
+			switch (id) {
+			case CLK_HDMI:
+				_hdmi_enable();
+				break;
+			case CLK_USB20:
+				return write<Clk_gate_ip_fsys::Usbhost20>(1);
+			case CLK_MMC0:
+				write<Clk_gate_ip_fsys::Sdmmc0>(1);
+				write<Clk_src_mask_fsys::Mmc0_mask>(1);
+				break;
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+		}
+
+		void _disable(Regulator_id id)
+		{
+			switch (id) {
+
+			case CLK_USB20:
+				return write<Clk_gate_ip_fsys::Usbhost20>(0);
+			case CLK_MMC0:
+				write<Clk_gate_ip_fsys::Sdmmc0>(0);
+				write<Clk_src_mask_fsys::Mmc0_mask>(0);
+				break;
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+		}
+
+	public:
+
+		/**
+		 * Constructor
+		 */
+		Cmu()
+		: Genode::Attached_mmio(Genode::Board_base::CMU_MMIO_BASE,
+		                        Genode::Board_base::CMU_MMIO_SIZE),
+		  _cpu_freq(CPU_FREQ_1600)
+		{
+			/**
+			 * Close certain clock gates by default (~ 0.7 Watt reduction)
+			 */
+			write<Clk_gate_ip_acp>(0);
+			write<Clk_gate_ip_isp0>(0);
+			write<Clk_gate_ip_isp1>(0);
+			write<Clk_gate_sclk_isp>(0);
+			write<Clk_gate_ip_gscl>(0);
+			write<Clk_gate_ip_disp1>(0);
+			write<Clk_gate_ip_mfc>(0);
+			write<Clk_gate_ip_g3d>(0);
+			write<Clk_gate_ip_gen>(0);
+			write<Clk_gate_ip_fsys>(0);
+			write<Clk_gate_ip_peric>(Clk_gate_ip_peric::Clk_uart2::bits(1) |
+			                         Clk_gate_ip_peric::Clk_pwm::bits(1));
+			write<Clk_gate_block>(Clk_gate_block::Clk_gen::bits(1));
+
+
+			/**
+			 * Set default CPU frequency
+			 */
+			_cpu_clk_freq(_cpu_freq);
+
+			/**
+			 * Hard wiring of certain reference clocks
+			 */
+			write<Pll_div2_sel::Mpll_fout_sel>(Pll_div2_sel::Mpll_fout_sel::MPLL_FOUT_HALF);
+			write<Clk_src_core1::Mux_mpll_sel>(Clk_src_core1::Mux_mpll_sel::MPLL_FOUT_RGT);
+			write<Clk_src_top2::Mux_mpll_user_sel>(Clk_src_top2::Mux_mpll_user_sel::MOUT_MPLL);
+			
+		}
+
+
+		/********************************
+		 ** Regulator driver interface **
+		 ********************************/
+
+		void level(Regulator_id id, unsigned long level)
+		{
+			switch (id) {
+			case CLK_CPU:
+				_cpu_clk_freq(level);
+				break;
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+		}
+
+		unsigned long level(Regulator_id id)
+		{
+			switch (id) {
+			case CLK_CPU:
+				return _cpu_freq;
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+			return 0;
+		}
+
+		void state(Regulator_id id, bool enable)
+		{
+			if (enable)
+				_enable(id);
+			else
+				_disable(id);
+		}
+
+		bool state(Regulator_id id)
+		{
+			switch (id) {
+
+			case CLK_USB20:
+				return read<Clk_gate_ip_fsys::Usbhost20>();
+			case CLK_MMC0:
+				return read<Clk_gate_ip_fsys::Sdmmc0>() &&
+				       read<Clk_src_mask_fsys::Mmc0_mask>();
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+			return true;
+		}
+};
+
+
+const Genode::uint8_t  Cmu::s_values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
+const Genode::uint16_t Cmu::m_values[] = { 100, 100, 200, 100, 125,
+                                           150, 175, 200, 425 };
+const Genode::uint8_t  Cmu::p_values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
+const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
+                                                       0x2147710, 0x2147710, 0x3157720,
+                                                       0x4167720, 0x4177730, 0x5377730 };
+#endif /* _CMU_H_ */
diff --git a/repos/os/src/drivers/platform/odroid-x2/main.cc b/repos/os/src/drivers/platform/odroid-x2/main.cc
new file mode 100644
index 0000000..1aaf6c2
--- /dev/null
+++ b/repos/os/src/drivers/platform/odroid-x2/main.cc
@@ -0,0 +1,65 @@
+/*
+ * \brief  Driver for Odroid-x2 specific platform devices (clocks, power, etc.)
+ * \author Alexy Gallardo Segura <al...@uclv.cu>
+ * \author Humberto Lopez Leon <humbe...@uclv.cu>
+ * \author Reinier Millo Sanchez <rmi...@uclv.cu>
+ * \date   2015-04-30
+ */
+
+/*
+ * Copyright (C) 2013 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#include <base/printf.h>
+#include <base/sleep.h>
+#include <cap_session/connection.h>
+#include <regulator/component.h>
+#include <regulator/consts.h>
+
+#include <cmu.h>
+#include <pmu.h>
+
+
+struct Driver_factory : Regulator::Driver_factory
+{
+	Cmu _cmu;
+	Pmu _pmu;
+
+	Regulator::Driver &create(Regulator::Regulator_id id) {
+		switch (id) {
+		case Regulator::CLK_CPU:
+		case Regulator::CLK_USB20:
+		case Regulator::CLK_MMC0:
+		case Regulator::CLK_HDMI:
+			return _cmu;
+		case Regulator::PWR_USB20:
+		case Regulator::PWR_HDMI:
+			return _pmu;
+		default:
+			throw Root::Invalid_args(); /* invalid regulator */
+		};
+	}
+
+	void destroy(Regulator::Driver &driver) { }
+
+};
+
+
+int main(int, char **)
+{
+	using namespace Genode;
+
+	PINF("--- Odroid-x2 platform driver ---\n");
+
+	static Cap_connection cap;
+	static Rpc_entrypoint ep(&cap, 4096, "odroid-x2_plat_ep");
+	static ::Driver_factory driver_factory;
+	static Regulator::Root reg_root(&ep, env()->heap(), driver_factory);
+	env()->parent()->announce(ep.manage(&reg_root));
+
+	sleep_forever();
+	return 0;
+}
diff --git a/repos/os/src/drivers/platform/odroid-x2/pmu.h b/repos/os/src/drivers/platform/odroid-x2/pmu.h
new file mode 100644
index 0000000..8505352
--- /dev/null
+++ b/repos/os/src/drivers/platform/odroid-x2/pmu.h
@@ -0,0 +1,219 @@
+/*
+ * \brief  Regulator driver for power management unit of Exynos4412 SoC
+ * \author Alexy Gallardo Segura <al...@uclv.cu>
+ * \author Humberto Lopez Leon <humbe...@uclv.cu>
+ * \author Reinier Millo Sanchez <rmi...@uclv.cu>
+ * \date   2015-04-30
+ */
+
+/*
+ * Copyright (C) 2013 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _PMU_H_
+#define _PMU_H_
+
+#include <regulator/consts.h>
+#include <regulator/driver.h>
+#include <drivers/board_base.h>
+#include <os/attached_mmio.h>
+
+using namespace Regulator;
+
+
+class Pmu : public Regulator::Driver,
+            public Genode::Attached_mmio
+{
+	private:
+
+		template <unsigned OFFSET>
+		struct Control : Register <OFFSET, 32>
+		{
+			struct Enable : Register<OFFSET, 32>::template Bitfield<0, 1> { };
+		};
+
+		template <unsigned OFFSET>
+		struct Configuration : Register <OFFSET, 32>
+		{
+			struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 3> { };
+		};
+
+		template <unsigned OFFSET>
+		struct Status : Register <OFFSET, 32>
+		{
+			struct Stat : Register<OFFSET, 32>::template Bitfield<0, 3> { };
+		};
+
+		template <unsigned OFFSET>
+		struct Sysclk_configuration : Register <OFFSET, 32>
+		{
+			struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 1> { };
+		};
+
+		template <unsigned OFFSET>
+		struct Sysclk_status : Register <OFFSET, 32>
+		{
+			struct Stat : Register<OFFSET, 32>::template Bitfield<0, 1> { };
+		};
+
+		struct Hdmi_phy_control : Register<0x700, 32>
+		{
+			struct Enable    : Bitfield<0, 1> { };
+			struct Div_ratio : Bitfield<16, 10> { };
+		};
+
+		typedef Control<0x704> Usbdrd_phy_control;
+		typedef Control<0x708> Usbhost_phy_control;
+		typedef Control<0x70c> Efnand_phy_control;
+		typedef Control<0x718> Adc_phy_control;
+		typedef Control<0x71c> Mtcadc_phy_control;
+		typedef Control<0x720> Dptx_phy_control;
+		typedef Control<0x724> Sata_phy_control;
+
+		typedef Sysclk_configuration<0x2a40> Vpll_sysclk_configuration;
+		typedef Sysclk_status<0x2a44>        Vpll_sysclk_status;
+		typedef Sysclk_configuration<0x2a60> Epll_sysclk_configuration;
+		typedef Sysclk_status<0x2a64>        Epll_sysclk_status;
+		typedef Sysclk_configuration<0x2aa0> Cpll_sysclk_configuration;
+		typedef Sysclk_status<0x2aa4>        Cpll_sysclk_status;
+		typedef Sysclk_configuration<0x2ac0> Gpll_sysclk_configuration;
+		typedef Sysclk_status<0x2ac4>        Gpll_sysclk_status;
+
+		typedef Configuration<0x4000> Gscl_configuration;
+		typedef Status<0x4004>        Gscl_status;
+		typedef Configuration<0x4020> Isp_configuration;
+		typedef Status<0x4024>        Isp_status;
+		typedef Configuration<0x4040> Mfc_configuration;
+		typedef Status<0x4044>        Mfc_status;
+		typedef Configuration<0x4060> G3d_configuration;
+		typedef Status<0x4064>        G3d_status;
+		typedef Configuration<0x40A0> Disp1_configuration;
+		typedef Status<0x40A4>        Disp1_status;
+		typedef Configuration<0x40C0> Mau_configuration;
+		typedef Status<0x40C4>        Mau_status;
+
+
+		template <typename C, typename S>
+		void _disable_domain()
+		{
+			if (read<typename S::Stat>() == 0)
+				return;
+			write<typename C::Local_pwr_cfg>(0);
+			while (read<typename S::Stat>() != 0) ;
+		}
+
+		template <typename C, typename S>
+		void _enable_domain()
+		{
+			if (read<typename S::Stat>() == 7)
+				return;
+			write<typename C::Local_pwr_cfg>(7);
+			while (read<typename S::Stat>() != 7) ;
+		}
+
+		void _enable(unsigned long id)
+		{
+			switch (id) {
+			case PWR_USB20:		//TODO keep USB and HDMI for future work
+				write<Usbhost_phy_control::Enable>(1);
+				break;
+			case PWR_HDMI: {
+				_enable_domain<Disp1_configuration, Disp1_status>();
+				Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
+				Hdmi_phy_control::Div_ratio::set(hpc, 150);
+				Hdmi_phy_control::Enable::set(hpc, 1);
+				write<Hdmi_phy_control>(hpc);
+				break; }
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+		}
+
+		void _disable(unsigned long id)
+		{
+			switch (id) {
+			case PWR_USB20:
+				write<Usbhost_phy_control::Enable>(0);
+				break;
+			default:      //TODO for hdmi case is missing 
+				PWRN("Unsupported for %s", names[id].name);
+			}
+		}
+
+	public:
+
+		/**
+		 * Constructor
+		 */
+		Pmu() : Genode::Attached_mmio(Genode::Board_base::PMU_MMIO_BASE,
+		                              Genode::Board_base::PMU_MMIO_SIZE)
+		{
+			write<Hdmi_phy_control   ::Enable>(0);
+			write<Usbdrd_phy_control ::Enable>(0);
+			write<Usbhost_phy_control::Enable>(0);
+			write<Efnand_phy_control ::Enable>(0);
+			write<Adc_phy_control    ::Enable>(0);
+			write<Mtcadc_phy_control ::Enable>(0);
+			write<Dptx_phy_control   ::Enable>(0);
+
+
+			_disable_domain<Gscl_configuration,  Gscl_status>();
+			_disable_domain<Isp_configuration,   Isp_status>();
+			_disable_domain<Mfc_configuration,   Mfc_status>();
+			_disable_domain<G3d_configuration,   G3d_status>();
+			_disable_domain<Disp1_configuration, Disp1_status>();
+			_disable_domain<Mau_configuration,   Mau_status>();
+
+			_disable_domain<Vpll_sysclk_configuration, Vpll_sysclk_status>();
+			_disable_domain<Epll_sysclk_configuration, Epll_sysclk_status>();
+			_disable_domain<Cpll_sysclk_configuration, Cpll_sysclk_status>();
+			_disable_domain<Gpll_sysclk_configuration, Gpll_sysclk_status>();
+		}
+
+
+		/********************************
+		 ** Regulator driver interface **
+		 ********************************/
+
+		void level(Regulator_id id, unsigned long level)
+		{
+			switch (id) {
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+		}
+
+		unsigned long level(Regulator_id id)
+		{
+			switch (id) {
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+			return 0;
+		}
+
+		void state(Regulator_id id, bool enable)
+		{
+			if (enable)
+				_enable(id);
+			else
+				_disable(id);
+		}
+
+		bool state(Regulator_id id)
+		{
+			switch (id) {
+			case PWR_USB20:
+				return read<Usbhost_phy_control::Enable>();
+			//TODO delete usb3 and sata cases
+			default:
+				PWRN("Unsupported for %s", names[id].name);
+			}
+			return true;
+		}
+};
+
+#endif /* _PMU_H_ */
diff --git a/repos/os/src/drivers/platform/odroid-x2/target.mk b/repos/os/src/drivers/platform/odroid-x2/target.mk
new file mode 100644
index 0000000..a61a42d
--- /dev/null
+++ b/repos/os/src/drivers/platform/odroid-x2/target.mk
@@ -0,0 +1,5 @@
+TARGET   = platform_drv
+REQUIRES = platform_odroid-x2
+SRC_CC   = main.cc
+INC_DIR += ${PRG_DIR}
+LIBS     = base
diff --git a/tool/builddir/etc/build.conf.foc_odroid-x2 b/tool/builddir/etc/build.conf.foc_odroid-x2
new file mode 100644
index 0000000..42bcc1c
--- /dev/null
+++ b/tool/builddir/etc/build.conf.foc_odroid-x2
@@ -0,0 +1,7 @@
+REPOSITORIES  = $(GENODE_DIR)/repos/base-foc
+
+##
+## Kernel-specific run tool configuration
+##
+
+RUN_OPT = --include boot_dir/foc
diff --git a/tool/create_builddir b/tool/create_builddir
index 2ba6757..91db01b 100755
--- a/tool/create_builddir
+++ b/tool/create_builddir
@@ -47,6 +47,7 @@ usage:
 	@echo "                  'foc_arndale'"
 	@echo "                  'sel4_x86_32'"
 	@echo "                  'lx_hybrid_x86'"
+	@echo "                  'foc_odroid-x2'"
 	@echo
 	@echo "  The definition of BUILD_DIR is optional. If specified,"
 	@echo "  <build-dir> is the location of the build directory to create."
@@ -145,7 +146,7 @@ $(BUILD_DIR)/Makefile:
 #
 # Add 'ports-foc' repository to Fiasco.OC build directory
 #
-ifeq ($(filter-out foc_x86_32 foc_imx53 foc_pbxa9 foc_vea9x4 foc_panda foc_arndale,$(PLATFORM)),)
+ifeq ($(filter-out foc_x86_32 foc_imx53 foc_pbxa9 foc_vea9x4 foc_panda foc_arndale foc_odroid-x2,$(PLATFORM)),)
 $(BUILD_DIR)/etc/build.conf::
 	@cat $(BUILD_CONF).ports-foc >> $@
 endif
@@ -161,7 +162,7 @@ endif
 #
 # Add ARM drivers repositories to ARM build directories
 #
-ifeq ($(filter-out foc_panda foc_arndale hw_panda hw_arndale hw_odroid_xu foc_imx53,$(PLATFORM)),)
+ifeq ($(filter-out foc_panda foc_arndale hw_panda hw_arndale hw_odroid_xu foc_imx53 foc_odroid-x2,$(PLATFORM)),)
 $(BUILD_DIR)/etc/build.conf::
 	@cat $(BUILD_CONF).drivers_arm >> $@
 endif
@@ -225,6 +226,10 @@ foc_arndale::
 	@echo "SPECS = genode foc_arndale" > $(BUILD_DIR)/etc/specs.conf
 	@echo "CROSS_DEV_PREFIX = /usr/local/genode-gcc/bin/genode-arm-" > $(BUILD_DIR)/etc/tools.conf
 
+foc_odroid-x2::
+	@echo "SPECS = genode foc_odroid-x2" > $(BUILD_DIR)/etc/specs.conf
+	@echo "CROSS_DEV_PREFIX = /usr/local/genode-gcc/bin/genode-arm-" > $(BUILD_DIR)/etc/tools.conf
+
 #
 # On all other platforms, the performance counter is assumed to be active by
 # default. On HW, its activation is done by an optional core lib. To be

<<attachment: rmillo.vcf>>
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