commit: f2f997ab5fd674039bdfa83e02eaaaceaf1de1b1 Author: Alice Ferrazzi <alicef <AT> gentoo <DOT> org> AuthorDate: Thu Jan 4 07:21:56 2018 +0000 Commit: Alice Ferrazzi <alicef <AT> gentoo <DOT> org> CommitDate: Thu Jan 4 07:21:56 2018 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=f2f997ab
x86/pti: Make sure the user/kernel PTEs match 0000_README | 4 ++ 1701_make_sure_the_user_kernel_PTEs_match.patch | 56 +++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/0000_README b/0000_README index 946c936..0cab5bc 100644 --- a/0000_README +++ b/0000_README @@ -99,6 +99,10 @@ Patch: 1700_do_not_enable_PTI_on_AMD_processor.patch From: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/patch/?id=694d99d40972f12e59a3696effee8a376b79d7c8 Desc: x86/cpu, x86/pti: Do not enable PTI on AMD processors. +Patch: 1701_make_sure_the_user_kernel_PTEs_match.patch +From: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/patch/?id=52994c256df36fda9a715697431cba9daecb6b11 +Desc: x86/pti: Make sure the user/kernel PTEs match + Patch: 2100_bcache-data-corruption-fix-for-bi-partno.patch From: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=62530ed8b1d07a45dec94d46e521c0c6c2d476e6 Desc: bio: ensure __bio_clone_fast copies bi_partno. diff --git a/1701_make_sure_the_user_kernel_PTEs_match.patch b/1701_make_sure_the_user_kernel_PTEs_match.patch new file mode 100644 index 0000000..601940b --- /dev/null +++ b/1701_make_sure_the_user_kernel_PTEs_match.patch @@ -0,0 +1,56 @@ +From 52994c256df36fda9a715697431cba9daecb6b11 Mon Sep 17 00:00:00 2001 +From: Thomas Gleixner <[email protected]> +Date: Wed, 3 Jan 2018 15:57:59 +0100 +Subject: x86/pti: Make sure the user/kernel PTEs match + +Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is +enabled: + +[Hardware Error]: Error Addr: 0x0000ffff81e000e0 +[Hardware Error]: MC1 Error: L1 TLB multimatch. +[Hardware Error]: cache level: L1, tx: INSN + +The address is in the entry area, which is mapped into kernel _AND_ user +space. That's special because we switch CR3 while we are executing +there. + +User mapping: +0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd + +Kernel mapping: +0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd + +So the K8 is complaining that the TLB entries differ. They differ in the +GLB bit. + +Drop the GLB bit when installing the user shared mapping. + +Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD") +Reported-by: Meelis Roos <[email protected]> +Signed-off-by: Thomas Gleixner <[email protected]> +Tested-by: Meelis Roos <[email protected]> +Cc: Borislav Petkov <[email protected]> +Cc: Tom Lendacky <[email protected]> +Cc: [email protected] +Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos +--- + arch/x86/mm/pti.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c +index bce8aea..2da28ba 100644 +--- a/arch/x86/mm/pti.c ++++ b/arch/x86/mm/pti.c +@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void) + static void __init pti_clone_entry_text(void) + { + pti_clone_pmds((unsigned long) __entry_text_start, +- (unsigned long) __irqentry_text_end, _PAGE_RW); ++ (unsigned long) __irqentry_text_end, ++ _PAGE_RW | _PAGE_GLOBAL); + } + + /* +-- +cgit v1.1 +
