commit: a7f6696c1a465601ed5aa37a060ec155e8e9ec85 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Tue Jul 17 10:24:44 2018 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Tue Jul 17 10:24:44 2018 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=a7f6696c
Linux patch 4.4.141 0000_README | 4 + 1140_linux-4.4.141.patch | 2989 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 2993 insertions(+) diff --git a/0000_README b/0000_README index 73e6c56..c1babcb 100644 --- a/0000_README +++ b/0000_README @@ -603,6 +603,10 @@ Patch: 1139_linux-4.4.140.patch From: http://www.kernel.org Desc: Linux 4.4.140 +Patch: 1140_linux-4.4.141.patch +From: http://www.kernel.org +Desc: Linux 4.4.141 + Patch: 1500_XATTR_USER_PREFIX.patch From: https://bugs.gentoo.org/show_bug.cgi?id=470644 Desc: Support for namespace user.pax.* on tmpfs. diff --git a/1140_linux-4.4.141.patch b/1140_linux-4.4.141.patch new file mode 100644 index 0000000..eec959a --- /dev/null +++ b/1140_linux-4.4.141.patch @@ -0,0 +1,2989 @@ +diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt +index 4df6bd7d01ed..e60d0b5809c1 100644 +--- a/Documentation/kernel-parameters.txt ++++ b/Documentation/kernel-parameters.txt +@@ -652,7 +652,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. + + clearcpuid=BITNUM [X86] + Disable CPUID feature X for the kernel. See +- arch/x86/include/asm/cpufeature.h for the valid bit ++ arch/x86/include/asm/cpufeatures.h for the valid bit + numbers. Note the Linux specific bits are not necessarily + stable over kernel options, but the vendor specific + ones should be. +diff --git a/Makefile b/Makefile +index b842298a5970..3fc39e41dbde 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,6 +1,6 @@ + VERSION = 4 + PATCHLEVEL = 4 +-SUBLEVEL = 140 ++SUBLEVEL = 141 + EXTRAVERSION = + NAME = Blurry Fish Butt + +diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c +index 8d5008cbdc0f..a853a83f2944 100644 +--- a/arch/mips/mm/ioremap.c ++++ b/arch/mips/mm/ioremap.c +@@ -9,6 +9,7 @@ + #include <linux/module.h> + #include <asm/addrspace.h> + #include <asm/byteorder.h> ++#include <linux/ioport.h> + #include <linux/sched.h> + #include <linux/slab.h> + #include <linux/vmalloc.h> +@@ -97,6 +98,20 @@ static int remap_area_pages(unsigned long address, phys_addr_t phys_addr, + return error; + } + ++static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages, ++ void *arg) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < nr_pages; i++) { ++ if (pfn_valid(start_pfn + i) && ++ !PageReserved(pfn_to_page(start_pfn + i))) ++ return 1; ++ } ++ ++ return 0; ++} ++ + /* + * Generic mapping function (not visible outside): + */ +@@ -115,8 +130,8 @@ static int remap_area_pages(unsigned long address, phys_addr_t phys_addr, + + void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long flags) + { ++ unsigned long offset, pfn, last_pfn; + struct vm_struct * area; +- unsigned long offset; + phys_addr_t last_addr; + void * addr; + +@@ -136,18 +151,16 @@ void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long + return (void __iomem *) CKSEG1ADDR(phys_addr); + + /* +- * Don't allow anybody to remap normal RAM that we're using.. ++ * Don't allow anybody to remap RAM that may be allocated by the page ++ * allocator, since that could lead to races & data clobbering. + */ +- if (phys_addr < virt_to_phys(high_memory)) { +- char *t_addr, *t_end; +- struct page *page; +- +- t_addr = __va(phys_addr); +- t_end = t_addr + (size - 1); +- +- for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++) +- if(!PageReserved(page)) +- return NULL; ++ pfn = PFN_DOWN(phys_addr); ++ last_pfn = PFN_DOWN(last_addr); ++ if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL, ++ __ioremap_check_ram) == 1) { ++ WARN_ONCE(1, "ioremap on RAM at %pa - %pa\n", ++ &phys_addr, &last_addr); ++ return NULL; + } + + /* +diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig +index eab1ef25eecd..d9afe6d40550 100644 +--- a/arch/x86/Kconfig ++++ b/arch/x86/Kconfig +@@ -346,6 +346,17 @@ config X86_FEATURE_NAMES + + If in doubt, say Y. + ++config X86_FAST_FEATURE_TESTS ++ bool "Fast CPU feature tests" if EMBEDDED ++ default y ++ ---help--- ++ Some fast-paths in the kernel depend on the capabilities of the CPU. ++ Say Y here for the kernel to patch in the appropriate code at runtime ++ based on the capabilities of the CPU. The infrastructure for patching ++ code at runtime takes up some additional space; space-constrained ++ embedded systems may wish to say N here to produce smaller, slightly ++ slower code. ++ + config X86_X2APIC + bool "Support x2apic" + depends on X86_LOCAL_APIC && X86_64 && (IRQ_REMAP || HYPERVISOR_GUEST) +diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug +index da00fe1f48f4..2aa212fb0faf 100644 +--- a/arch/x86/Kconfig.debug ++++ b/arch/x86/Kconfig.debug +@@ -367,16 +367,6 @@ config DEBUG_IMR_SELFTEST + + If unsure say N here. + +-config X86_DEBUG_STATIC_CPU_HAS +- bool "Debug alternatives" +- depends on DEBUG_KERNEL +- ---help--- +- This option causes additional code to be generated which +- fails if static_cpu_has() is used before alternatives have +- run. +- +- If unsure, say N. +- + config X86_DEBUG_FPU + bool "Debug the x86 FPU code" + depends on DEBUG_KERNEL +diff --git a/arch/x86/boot/cpuflags.h b/arch/x86/boot/cpuflags.h +index ea97697e51e4..4cb404fd45ce 100644 +--- a/arch/x86/boot/cpuflags.h ++++ b/arch/x86/boot/cpuflags.h +@@ -1,7 +1,7 @@ + #ifndef BOOT_CPUFLAGS_H + #define BOOT_CPUFLAGS_H + +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/processor-flags.h> + + struct cpu_features { +diff --git a/arch/x86/boot/mkcpustr.c b/arch/x86/boot/mkcpustr.c +index 637097e66a62..f72498dc90d2 100644 +--- a/arch/x86/boot/mkcpustr.c ++++ b/arch/x86/boot/mkcpustr.c +@@ -17,7 +17,7 @@ + + #include "../include/asm/required-features.h" + #include "../include/asm/disabled-features.h" +-#include "../include/asm/cpufeature.h" ++#include "../include/asm/cpufeatures.h" + #include "../kernel/cpu/capflags.c" + + int main(void) +diff --git a/arch/x86/crypto/crc32-pclmul_glue.c b/arch/x86/crypto/crc32-pclmul_glue.c +index 07d2c6c86a54..27226df3f7d8 100644 +--- a/arch/x86/crypto/crc32-pclmul_glue.c ++++ b/arch/x86/crypto/crc32-pclmul_glue.c +@@ -33,7 +33,7 @@ + #include <linux/crc32.h> + #include <crypto/internal/hash.h> + +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/cpu_device_id.h> + #include <asm/fpu/api.h> + +diff --git a/arch/x86/crypto/crc32c-intel_glue.c b/arch/x86/crypto/crc32c-intel_glue.c +index 15f5c7675d42..715399b14ed7 100644 +--- a/arch/x86/crypto/crc32c-intel_glue.c ++++ b/arch/x86/crypto/crc32c-intel_glue.c +@@ -30,7 +30,7 @@ + #include <linux/kernel.h> + #include <crypto/internal/hash.h> + +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/cpu_device_id.h> + #include <asm/fpu/internal.h> + +diff --git a/arch/x86/crypto/crct10dif-pclmul_glue.c b/arch/x86/crypto/crct10dif-pclmul_glue.c +index a3fcfc97a311..cd4df9322501 100644 +--- a/arch/x86/crypto/crct10dif-pclmul_glue.c ++++ b/arch/x86/crypto/crct10dif-pclmul_glue.c +@@ -30,7 +30,7 @@ + #include <linux/string.h> + #include <linux/kernel.h> + #include <asm/fpu/api.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/cpu_device_id.h> + + asmlinkage __u16 crc_t10dif_pcl(__u16 crc, const unsigned char *buf, +diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c +index b5eb1cca70a0..071582a3b5c0 100644 +--- a/arch/x86/entry/common.c ++++ b/arch/x86/entry/common.c +@@ -27,6 +27,7 @@ + #include <asm/traps.h> + #include <asm/vdso.h> + #include <asm/uaccess.h> ++#include <asm/cpufeature.h> + + #define CREATE_TRACE_POINTS + #include <trace/events/syscalls.h> +diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S +index d437f3871e53..49a8c9f7a379 100644 +--- a/arch/x86/entry/entry_32.S ++++ b/arch/x86/entry/entry_32.S +@@ -40,7 +40,7 @@ + #include <asm/processor-flags.h> + #include <asm/ftrace.h> + #include <asm/irq_vectors.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + #include <asm/asm.h> + #include <asm/smap.h> +diff --git a/arch/x86/entry/vdso/vdso32-setup.c b/arch/x86/entry/vdso/vdso32-setup.c +index a7508d7e20b7..3f9d1a83891a 100644 +--- a/arch/x86/entry/vdso/vdso32-setup.c ++++ b/arch/x86/entry/vdso/vdso32-setup.c +@@ -11,7 +11,6 @@ + #include <linux/kernel.h> + #include <linux/mm_types.h> + +-#include <asm/cpufeature.h> + #include <asm/processor.h> + #include <asm/vdso.h> + +diff --git a/arch/x86/entry/vdso/vdso32/system_call.S b/arch/x86/entry/vdso/vdso32/system_call.S +index 3a1d9297074b..0109ac6cb79c 100644 +--- a/arch/x86/entry/vdso/vdso32/system_call.S ++++ b/arch/x86/entry/vdso/vdso32/system_call.S +@@ -3,7 +3,7 @@ + */ + + #include <asm/dwarf2.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + + /* +diff --git a/arch/x86/entry/vdso/vma.c b/arch/x86/entry/vdso/vma.c +index b8f69e264ac4..6b46648588d8 100644 +--- a/arch/x86/entry/vdso/vma.c ++++ b/arch/x86/entry/vdso/vma.c +@@ -20,6 +20,7 @@ + #include <asm/page.h> + #include <asm/hpet.h> + #include <asm/desc.h> ++#include <asm/cpufeature.h> + + #if defined(CONFIG_X86_64) + unsigned int __read_mostly vdso64_enabled = 1; +@@ -254,7 +255,7 @@ static void vgetcpu_cpu_init(void *arg) + #ifdef CONFIG_NUMA + node = cpu_to_node(cpu); + #endif +- if (cpu_has(&cpu_data(cpu), X86_FEATURE_RDTSCP)) ++ if (static_cpu_has(X86_FEATURE_RDTSCP)) + write_rdtscp_aux((node << 12) | cpu); + + /* +diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h +index 215ea9214215..002fcd901f07 100644 +--- a/arch/x86/include/asm/alternative.h ++++ b/arch/x86/include/asm/alternative.h +@@ -153,12 +153,6 @@ static inline int alternatives_text_reserved(void *start, void *end) + ALTINSTR_REPLACEMENT(newinstr2, feature2, 2) \ + ".popsection\n" + +-/* +- * This must be included *after* the definition of ALTERNATIVE due to +- * <asm/arch_hweight.h> +- */ +-#include <asm/cpufeature.h> +- + /* + * Alternative instructions for different CPU types or capabilities. + * +diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h +index 163769d82475..fd810a57ab1b 100644 +--- a/arch/x86/include/asm/apic.h ++++ b/arch/x86/include/asm/apic.h +@@ -6,7 +6,6 @@ + + #include <asm/alternative.h> + #include <asm/cpufeature.h> +-#include <asm/processor.h> + #include <asm/apicdef.h> + #include <linux/atomic.h> + #include <asm/fixmap.h> +diff --git a/arch/x86/include/asm/arch_hweight.h b/arch/x86/include/asm/arch_hweight.h +index 44f825c80ed5..e7cd63175de4 100644 +--- a/arch/x86/include/asm/arch_hweight.h ++++ b/arch/x86/include/asm/arch_hweight.h +@@ -1,6 +1,8 @@ + #ifndef _ASM_X86_HWEIGHT_H + #define _ASM_X86_HWEIGHT_H + ++#include <asm/cpufeatures.h> ++ + #ifdef CONFIG_64BIT + /* popcnt %edi, %eax */ + #define POPCNT32 ".byte 0xf3,0x0f,0xb8,0xc7" +diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h +index ae5fb83e6d91..3e8674288198 100644 +--- a/arch/x86/include/asm/atomic.h ++++ b/arch/x86/include/asm/atomic.h +@@ -3,7 +3,6 @@ + + #include <linux/compiler.h> + #include <linux/types.h> +-#include <asm/processor.h> + #include <asm/alternative.h> + #include <asm/cmpxchg.h> + #include <asm/rmwcc.h> +diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h +index a11c30b77fb5..a984111135b1 100644 +--- a/arch/x86/include/asm/atomic64_32.h ++++ b/arch/x86/include/asm/atomic64_32.h +@@ -3,7 +3,6 @@ + + #include <linux/compiler.h> + #include <linux/types.h> +-#include <asm/processor.h> + //#include <asm/cmpxchg.h> + + /* An 64bit atomic type */ +diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h +index ad19841eddfe..9733361fed6f 100644 +--- a/arch/x86/include/asm/cmpxchg.h ++++ b/arch/x86/include/asm/cmpxchg.h +@@ -2,6 +2,7 @@ + #define ASM_X86_CMPXCHG_H + + #include <linux/compiler.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative.h> /* Provides LOCK_PREFIX */ + + /* +diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h +index 232621c5e859..dd0089841a0f 100644 +--- a/arch/x86/include/asm/cpufeature.h ++++ b/arch/x86/include/asm/cpufeature.h +@@ -1,294 +1,35 @@ +-/* +- * Defines x86 CPU feature bits +- */ + #ifndef _ASM_X86_CPUFEATURE_H + #define _ASM_X86_CPUFEATURE_H + +-#ifndef _ASM_X86_REQUIRED_FEATURES_H +-#include <asm/required-features.h> +-#endif +- +-#ifndef _ASM_X86_DISABLED_FEATURES_H +-#include <asm/disabled-features.h> +-#endif +- +-#define NCAPINTS 14 /* N 32-bit words worth of info */ +-#define NBUGINTS 1 /* N 32-bit bug flags */ +- +-/* +- * Note: If the comment begins with a quoted string, that string is used +- * in /proc/cpuinfo instead of the macro name. If the string is "", +- * this feature bit is not displayed in /proc/cpuinfo at all. +- */ +- +-/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ +-#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ +-#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ +-#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ +-#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ +-#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ +-#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ +-#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ +-#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ +-#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ +-#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ +-#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ +-#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ +-#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ +-#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ +-#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ +- /* (plus FCMOVcc, FCOMI with FPU) */ +-#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ +-#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ +-#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ +-#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ +-#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ +-#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ +-#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ +-#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ +-#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ +-#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ +-#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ +-#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ +-#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ +-#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ +-#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ +- +-/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ +-/* Don't duplicate feature flags which are redundant with Intel! */ +-#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ +-#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ +-#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ +-#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ +-#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ +-#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ +-#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ +-#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ +-#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ +-#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ +- +-/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ +-#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ +-#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ +-#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ +- +-/* Other features, Linux-defined mapping, word 3 */ +-/* This range is used for feature bits which conflict or are synthesized */ +-#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ +-#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ +-#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ +-#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ +-/* cpu types for specific tunings: */ +-#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ +-#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ +-#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ +-#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ +-#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ +-#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ +-/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ +-#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ +-#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ +-#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ +-#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ +-#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ +-#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ +-#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ +-#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ +-/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ +-#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ +-#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ +-#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ +-#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ +-#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ +-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ +-#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ +-#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ +-#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ +-/* free, was #define X86_FEATURE_EAGER_FPU ( 3*32+29) * "eagerfpu" Non lazy FPU restore */ +-#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ +- +-/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ +-#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ +-#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ +-#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ +-#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ +-#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ +-#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ +-#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ +-#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ +-#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ +-#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ +-#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ +-#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ +-#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ +-#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ +-#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ +-#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ +-#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ +-#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ +-#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ +-#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ +-#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ +-#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ +-#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ +-#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ +-#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ +-#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ +-#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ +-#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ +-#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ +-#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ +-#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ +- +-/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ +-#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ +-#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ +-#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ +-#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ +-#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ +-#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ +-#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ +-#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ +-#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ +-#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ +- +-/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ +-#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ +-#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ +-#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ +-#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ +-#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ +-#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ +-#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ +-#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ +-#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ +-#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ +-#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ +-#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ +-#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ +-#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ +-#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ +-#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ +-#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ +-#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ +-#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ +-#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ +-#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ +-#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ +-#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ +-#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +-#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ +- +-/* +- * Auxiliary flags: Linux defined - For features scattered in various +- * CPUID levels like 0x6, 0xA etc, word 7 +- */ +-#define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ +-#define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ +-#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ +-#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ +-#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */ +-#define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ +-#define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ +-#define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ +-#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ +-#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ +-#define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ +-#define X86_FEATURE_HWP_NOTIFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ +-#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ +-#define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ +-#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ +-#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ +-#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ +- +-#define X86_FEATURE_RETPOLINE ( 7*32+29) /* Generic Retpoline mitigation for Spectre variant 2 */ +-#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* AMD Retpoline mitigation for Spectre variant 2 */ +-/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */ +-#define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */ +- +-/* Virtualization flags: Linux defined, word 8 */ +-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ +-#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ +-#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ +-#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ +-#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ +-#define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ +-#define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ +-#define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ +-#define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ +-#define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ +-#define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ +-#define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ +-#define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ +-#define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ +-#define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ +-#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ +-#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ +- +- +-/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ +-#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ +-#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ +-#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ +-#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ +-#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ +-#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ +-#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ +-#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ +-#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ +-#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ +-#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ +-#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ +-#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ +-#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ +-#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ +-#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ +-#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ +-#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ +-#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ +-#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ +-#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ +-#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +-#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ +- +-/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ +-#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ +-#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ +-#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ +-#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ +- +-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ +-#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ +- +-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ +-#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +- +-/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ +-#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ +- +-/* +- * BUG word(s) +- */ +-#define X86_BUG(x) (NCAPINTS*32 + (x)) +- +-#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ +-#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ +-#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ +-#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ +-#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ +-#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ +-#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ +-#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ +-#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ +-#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ +-#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ +-#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ ++#include <asm/processor.h> + + #if defined(__KERNEL__) && !defined(__ASSEMBLY__) + + #include <asm/asm.h> + #include <linux/bitops.h> + ++enum cpuid_leafs ++{ ++ CPUID_1_EDX = 0, ++ CPUID_8000_0001_EDX, ++ CPUID_8086_0001_EDX, ++ CPUID_LNX_1, ++ CPUID_1_ECX, ++ CPUID_C000_0001_EDX, ++ CPUID_8000_0001_ECX, ++ CPUID_LNX_2, ++ CPUID_LNX_3, ++ CPUID_7_0_EBX, ++ CPUID_D_1_EAX, ++ CPUID_F_0_EDX, ++ CPUID_F_1_EDX, ++ CPUID_8000_0008_EBX, ++ CPUID_6_EAX, ++ CPUID_8000_000A_EDX, ++ CPUID_7_ECX, ++ CPUID_8000_0007_EBX, ++}; ++ + #ifdef CONFIG_X86_FEATURE_NAMES + extern const char * const x86_cap_flags[NCAPINTS*32]; + extern const char * const x86_power_flags[32]; +@@ -308,29 +49,59 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; + #define test_cpu_cap(c, bit) \ + test_bit(bit, (unsigned long *)((c)->x86_capability)) + +-#define REQUIRED_MASK_BIT_SET(bit) \ +- ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ +- (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ +- (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ +- (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ +- (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ +- (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ +- (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ +- (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ +- (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ +- (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) +- +-#define DISABLED_MASK_BIT_SET(bit) \ +- ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \ +- (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \ +- (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \ +- (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \ +- (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \ +- (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \ +- (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \ +- (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \ +- (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \ +- (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) ) ++/* ++ * There are 32 bits/features in each mask word. The high bits ++ * (selected with (bit>>5) give us the word number and the low 5 ++ * bits give us the bit/feature number inside the word. ++ * (1UL<<((bit)&31) gives us a mask for the feature_bit so we can ++ * see if it is set in the mask word. ++ */ ++#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \ ++ (((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word )) ++ ++#define REQUIRED_MASK_BIT_SET(feature_bit) \ ++ ( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 2, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 3, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 4, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 5, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 6, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 7, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 8, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 9, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 10, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 11, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 12, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 13, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 14, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ ++ REQUIRED_MASK_CHECK || \ ++ BUILD_BUG_ON_ZERO(NCAPINTS != 18)) ++ ++#define DISABLED_MASK_BIT_SET(feature_bit) \ ++ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 1, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 2, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 3, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 4, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 5, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 6, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 7, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 8, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 9, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 10, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 11, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 12, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 13, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 14, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \ ++ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ ++ DISABLED_MASK_CHECK || \ ++ BUILD_BUG_ON_ZERO(NCAPINTS != 18)) + + #define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ +@@ -349,8 +120,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; + * is not relevant. + */ + #define cpu_feature_enabled(bit) \ +- (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \ +- cpu_has(&boot_cpu_data, bit)) ++ (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit)) + + #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) + +@@ -388,106 +158,19 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; + #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) + #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) + /* +- * Do not add any more of those clumsy macros - use static_cpu_has_safe() for ++ * Do not add any more of those clumsy macros - use static_cpu_has() for + * fast paths and boot_cpu_has() otherwise! + */ + +-#if __GNUC__ >= 4 +-extern void warn_pre_alternatives(void); +-extern bool __static_cpu_has_safe(u16 bit); +- ++#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS) + /* + * Static testing of CPU features. Used the same as boot_cpu_has(). +- * These are only valid after alternatives have run, but will statically +- * patch the target code for additional performance. ++ * These will statically patch the target code for additional ++ * performance. + */ +-static __always_inline __pure bool __static_cpu_has(u16 bit) +-{ +-#ifdef CC_HAVE_ASM_GOTO +- +-#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS +- +- /* +- * Catch too early usage of this before alternatives +- * have run. +- */ +- asm_volatile_goto("1: jmp %l[t_warn]\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" +- " .long 0\n" /* no replacement */ +- " .word %P0\n" /* 1: do replace */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 0\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- /* skipping size check since replacement size = 0 */ +- : : "i" (X86_FEATURE_ALWAYS) : : t_warn); +- +-#endif +- +- asm_volatile_goto("1: jmp %l[t_no]\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" +- " .long 0\n" /* no replacement */ +- " .word %P0\n" /* feature bit */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 0\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- /* skipping size check since replacement size = 0 */ +- : : "i" (bit) : : t_no); +- return true; +- t_no: +- return false; +- +-#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS +- t_warn: +- warn_pre_alternatives(); +- return false; +-#endif +- +-#else /* CC_HAVE_ASM_GOTO */ +- +- u8 flag; +- /* Open-coded due to __stringify() in ALTERNATIVE() */ +- asm volatile("1: movb $0,%0\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" +- " .long 3f - .\n" +- " .word %P1\n" /* feature bit */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 4f - 3f\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- ".section .discard,\"aw\",@progbits\n" +- " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ +- ".previous\n" +- ".section .altinstr_replacement,\"ax\"\n" +- "3: movb $1,%0\n" +- "4:\n" +- ".previous\n" +- : "=qm" (flag) : "i" (bit)); +- return flag; +- +-#endif /* CC_HAVE_ASM_GOTO */ +-} +- +-#define static_cpu_has(bit) \ +-( \ +- __builtin_constant_p(boot_cpu_has(bit)) ? \ +- boot_cpu_has(bit) : \ +- __builtin_constant_p(bit) ? \ +- __static_cpu_has(bit) : \ +- boot_cpu_has(bit) \ +-) +- +-static __always_inline __pure bool _static_cpu_has_safe(u16 bit) ++static __always_inline __pure bool _static_cpu_has(u16 bit) + { +-#ifdef CC_HAVE_ASM_GOTO +- asm_volatile_goto("1: jmp %l[t_dynamic]\n" ++ asm_volatile_goto("1: jmp 6f\n" + "2:\n" + ".skip -(((5f-4f) - (2b-1b)) > 0) * " + "((5f-4f) - (2b-1b)),0x90\n" +@@ -512,66 +195,34 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit) + " .byte 0\n" /* repl len */ + " .byte 0\n" /* pad len */ + ".previous\n" +- : : "i" (bit), "i" (X86_FEATURE_ALWAYS) +- : : t_dynamic, t_no); ++ ".section .altinstr_aux,\"ax\"\n" ++ "6:\n" ++ " testb %[bitnum],%[cap_byte]\n" ++ " jnz %l[t_yes]\n" ++ " jmp %l[t_no]\n" ++ ".previous\n" ++ : : "i" (bit), "i" (X86_FEATURE_ALWAYS), ++ [bitnum] "i" (1 << (bit & 7)), ++ [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3]) ++ : : t_yes, t_no); ++ t_yes: + return true; + t_no: + return false; +- t_dynamic: +- return __static_cpu_has_safe(bit); +-#else +- u8 flag; +- /* Open-coded due to __stringify() in ALTERNATIVE() */ +- asm volatile("1: movb $2,%0\n" +- "2:\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" /* src offset */ +- " .long 3f - .\n" /* repl offset */ +- " .word %P2\n" /* always replace */ +- " .byte 2b - 1b\n" /* source len */ +- " .byte 4f - 3f\n" /* replacement len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- ".section .discard,\"aw\",@progbits\n" +- " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ +- ".previous\n" +- ".section .altinstr_replacement,\"ax\"\n" +- "3: movb $0,%0\n" +- "4:\n" +- ".previous\n" +- ".section .altinstructions,\"a\"\n" +- " .long 1b - .\n" /* src offset */ +- " .long 5f - .\n" /* repl offset */ +- " .word %P1\n" /* feature bit */ +- " .byte 4b - 3b\n" /* src len */ +- " .byte 6f - 5f\n" /* repl len */ +- " .byte 0\n" /* pad len */ +- ".previous\n" +- ".section .discard,\"aw\",@progbits\n" +- " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ +- ".previous\n" +- ".section .altinstr_replacement,\"ax\"\n" +- "5: movb $1,%0\n" +- "6:\n" +- ".previous\n" +- : "=qm" (flag) +- : "i" (bit), "i" (X86_FEATURE_ALWAYS)); +- return (flag == 2 ? __static_cpu_has_safe(bit) : flag); +-#endif /* CC_HAVE_ASM_GOTO */ + } + +-#define static_cpu_has_safe(bit) \ ++#define static_cpu_has(bit) \ + ( \ + __builtin_constant_p(boot_cpu_has(bit)) ? \ + boot_cpu_has(bit) : \ +- _static_cpu_has_safe(bit) \ ++ _static_cpu_has(bit) \ + ) + #else + /* +- * gcc 3.x is too stupid to do the static test; fall back to dynamic. ++ * Fall back to dynamic for gcc versions which don't support asm goto. Should be ++ * a minority now anyway. + */ + #define static_cpu_has(bit) boot_cpu_has(bit) +-#define static_cpu_has_safe(bit) boot_cpu_has(bit) + #endif + + #define cpu_has_bug(c, bit) cpu_has(c, (bit)) +@@ -579,7 +230,6 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit) + #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) + + #define static_cpu_has_bug(bit) static_cpu_has((bit)) +-#define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit)) + #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) + + #define MAX_CPU_FEATURES (NCAPINTS * 32) +diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h +new file mode 100644 +index 000000000000..205ce70c1d6c +--- /dev/null ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -0,0 +1,306 @@ ++#ifndef _ASM_X86_CPUFEATURES_H ++#define _ASM_X86_CPUFEATURES_H ++ ++#ifndef _ASM_X86_REQUIRED_FEATURES_H ++#include <asm/required-features.h> ++#endif ++ ++#ifndef _ASM_X86_DISABLED_FEATURES_H ++#include <asm/disabled-features.h> ++#endif ++ ++/* ++ * Defines x86 CPU feature bits ++ */ ++#define NCAPINTS 18 /* N 32-bit words worth of info */ ++#define NBUGINTS 1 /* N 32-bit bug flags */ ++ ++/* ++ * Note: If the comment begins with a quoted string, that string is used ++ * in /proc/cpuinfo instead of the macro name. If the string is "", ++ * this feature bit is not displayed in /proc/cpuinfo at all. ++ */ ++ ++/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ ++#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ ++#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ ++#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ ++#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ ++#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ ++#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ ++#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ ++#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ ++#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ ++#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ ++#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ ++#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ ++#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ ++#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ ++#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ ++ /* (plus FCMOVcc, FCOMI with FPU) */ ++#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ ++#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ ++#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ ++#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ ++#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ ++#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ ++#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ ++#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ ++#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ ++#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ ++#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ ++#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ ++#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ ++#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ ++#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ ++ ++/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ ++/* Don't duplicate feature flags which are redundant with Intel! */ ++#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ ++#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ ++#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ ++#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ ++#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ ++#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ ++#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ ++#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ ++#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ ++#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ ++ ++/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ ++#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ ++#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ ++#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ ++ ++/* Other features, Linux-defined mapping, word 3 */ ++/* This range is used for feature bits which conflict or are synthesized */ ++#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ ++#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ ++#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ ++#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ ++/* cpu types for specific tunings: */ ++#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ ++#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ ++#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ ++#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ ++#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ ++#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ ++/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ ++#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ ++#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ ++#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ ++#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ ++#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ ++#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ ++#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ ++#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ ++/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ ++#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ ++#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ ++#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ ++#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ ++#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ ++/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ ++#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ ++#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ ++#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ ++/* free, was #define X86_FEATURE_EAGER_FPU ( 3*32+29) * "eagerfpu" Non lazy FPU restore */ ++#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ ++ ++/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ ++#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ ++#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ ++#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ ++#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ ++#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ ++#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ ++#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ ++#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ ++#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ ++#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ ++#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ ++#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ ++#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ ++#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ ++#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ ++#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ ++#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ ++#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ ++#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ ++#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ ++#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ ++#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ ++#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ ++#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ ++#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ ++#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ ++#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ ++#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ ++#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ ++#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ ++#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ ++ ++/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ ++#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ ++#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ ++#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ ++#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ ++#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ ++#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ ++#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ ++#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ ++#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ ++#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ ++ ++/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ ++#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ ++#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ ++#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ ++#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ ++#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ ++#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ ++#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ ++#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ ++#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ ++#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ ++#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ ++#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ ++#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ ++#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ ++#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ ++#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ ++#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ ++#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ ++#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ ++#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ ++#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ ++#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ ++#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ ++#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ ++#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ ++ ++/* ++ * Auxiliary flags: Linux defined - For features scattered in various ++ * CPUID levels like 0x6, 0xA etc, word 7. ++ * ++ * Reuse free bits when adding new feature flags! ++ */ ++ ++#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ ++#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ ++#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */ ++ ++#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ ++#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ ++ ++#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ ++#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ ++ ++#define X86_FEATURE_RETPOLINE ( 7*32+29) /* Generic Retpoline mitigation for Spectre variant 2 */ ++#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* AMD Retpoline mitigation for Spectre variant 2 */ ++/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */ ++#define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */ ++ ++/* Virtualization flags: Linux defined, word 8 */ ++#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ ++#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ ++#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ ++#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ ++#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ ++ ++#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ ++#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ ++ ++ ++/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ ++#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ ++#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ ++#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ ++#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ ++#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ ++#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ ++#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ ++#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ ++#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ ++#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ ++#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ ++#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ ++#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ ++#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ ++#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ ++#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ ++#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ ++#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ ++#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ ++#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ ++#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ ++#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ ++#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ ++ ++/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ ++#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ ++#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ ++#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ ++#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ ++ ++/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ ++#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ ++ ++/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ ++#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ ++ ++/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ ++#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ ++ ++/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ ++#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ ++#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ ++#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ ++#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ ++#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ ++#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ ++#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ ++#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ ++#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ ++#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ ++ ++/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ ++#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ ++#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ ++#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ ++#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ ++#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ ++#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ ++#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ ++#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ ++#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ ++#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ ++ ++/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ ++#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ ++#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ ++ ++/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ ++#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ ++#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ ++#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ ++ ++/* ++ * BUG word(s) ++ */ ++#define X86_BUG(x) (NCAPINTS*32 + (x)) ++ ++#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ ++#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ ++#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ ++#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ ++#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ ++#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ ++#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ ++#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ ++#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ ++#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ ++#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ ++#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ ++ ++#endif /* _ASM_X86_CPUFEATURES_H */ +diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h +index 8b17c2ad1048..21c5ac15657b 100644 +--- a/arch/x86/include/asm/disabled-features.h ++++ b/arch/x86/include/asm/disabled-features.h +@@ -30,6 +30,14 @@ + # define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) + #endif /* CONFIG_X86_64 */ + ++#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS ++# define DISABLE_PKU 0 ++# define DISABLE_OSPKE 0 ++#else ++# define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) ++# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) ++#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ ++ + /* + * Make sure to add features to the correct mask + */ +@@ -43,5 +51,14 @@ + #define DISABLED_MASK7 0 + #define DISABLED_MASK8 0 + #define DISABLED_MASK9 (DISABLE_MPX) ++#define DISABLED_MASK10 0 ++#define DISABLED_MASK11 0 ++#define DISABLED_MASK12 0 ++#define DISABLED_MASK13 0 ++#define DISABLED_MASK14 0 ++#define DISABLED_MASK15 0 ++#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE) ++#define DISABLED_MASK17 0 ++#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) + + #endif /* _ASM_X86_DISABLED_FEATURES_H */ +diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h +index 146d838e6ee7..ec2aedb6f92a 100644 +--- a/arch/x86/include/asm/fpu/internal.h ++++ b/arch/x86/include/asm/fpu/internal.h +@@ -17,6 +17,7 @@ + #include <asm/user.h> + #include <asm/fpu/api.h> + #include <asm/fpu/xstate.h> ++#include <asm/cpufeature.h> + + /* + * High level FPU state handling functions: +@@ -63,17 +64,17 @@ static __always_inline __pure bool use_eager_fpu(void) + + static __always_inline __pure bool use_xsaveopt(void) + { +- return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); ++ return static_cpu_has(X86_FEATURE_XSAVEOPT); + } + + static __always_inline __pure bool use_xsave(void) + { +- return static_cpu_has_safe(X86_FEATURE_XSAVE); ++ return static_cpu_has(X86_FEATURE_XSAVE); + } + + static __always_inline __pure bool use_fxsr(void) + { +- return static_cpu_has_safe(X86_FEATURE_FXSR); ++ return static_cpu_has(X86_FEATURE_FXSR); + } + + /* +@@ -225,18 +226,67 @@ static inline void copy_fxregs_to_kernel(struct fpu *fpu) + #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f" + #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f" + +-/* xstate instruction fault handler: */ +-#define xstate_fault(__err) \ +- \ +- ".section .fixup,\"ax\"\n" \ +- \ +- "3: movl $-2,%[_err]\n" \ +- " jmp 2b\n" \ +- \ +- ".previous\n" \ +- \ +- _ASM_EXTABLE(1b, 3b) \ +- : [_err] "=r" (__err) ++#define XSTATE_OP(op, st, lmask, hmask, err) \ ++ asm volatile("1:" op "\n\t" \ ++ "xor %[err], %[err]\n" \ ++ "2:\n\t" \ ++ ".pushsection .fixup,\"ax\"\n\t" \ ++ "3: movl $-2,%[err]\n\t" \ ++ "jmp 2b\n\t" \ ++ ".popsection\n\t" \ ++ _ASM_EXTABLE(1b, 3b) \ ++ : [err] "=r" (err) \ ++ : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ ++ : "memory") ++ ++/* ++ * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact ++ * format and supervisor states in addition to modified optimization in ++ * XSAVEOPT. ++ * ++ * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT ++ * supports modified optimization which is not supported by XSAVE. ++ * ++ * We use XSAVE as a fallback. ++ * ++ * The 661 label is defined in the ALTERNATIVE* macros as the address of the ++ * original instruction which gets replaced. We need to use it here as the ++ * address of the instruction where we might get an exception at. ++ */ ++#define XSTATE_XSAVE(st, lmask, hmask, err) \ ++ asm volatile(ALTERNATIVE_2(XSAVE, \ ++ XSAVEOPT, X86_FEATURE_XSAVEOPT, \ ++ XSAVES, X86_FEATURE_XSAVES) \ ++ "\n" \ ++ "xor %[err], %[err]\n" \ ++ "3:\n" \ ++ ".pushsection .fixup,\"ax\"\n" \ ++ "4: movl $-2, %[err]\n" \ ++ "jmp 3b\n" \ ++ ".popsection\n" \ ++ _ASM_EXTABLE(661b, 4b) \ ++ : [err] "=r" (err) \ ++ : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ ++ : "memory") ++ ++/* ++ * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact ++ * XSAVE area format. ++ */ ++#define XSTATE_XRESTORE(st, lmask, hmask, err) \ ++ asm volatile(ALTERNATIVE(XRSTOR, \ ++ XRSTORS, X86_FEATURE_XSAVES) \ ++ "\n" \ ++ "xor %[err], %[err]\n" \ ++ "3:\n" \ ++ ".pushsection .fixup,\"ax\"\n" \ ++ "4: movl $-2, %[err]\n" \ ++ "jmp 3b\n" \ ++ ".popsection\n" \ ++ _ASM_EXTABLE(661b, 4b) \ ++ : [err] "=r" (err) \ ++ : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ ++ : "memory") + + /* + * This function is called only during boot time when x86 caps are not set +@@ -247,22 +297,14 @@ static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate) + u64 mask = -1; + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + + WARN_ON(system_state != SYSTEM_BOOTING); + +- if (boot_cpu_has(X86_FEATURE_XSAVES)) +- asm volatile("1:"XSAVES"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ if (static_cpu_has(X86_FEATURE_XSAVES)) ++ XSTATE_OP(XSAVES, xstate, lmask, hmask, err); + else +- asm volatile("1:"XSAVE"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ XSTATE_OP(XSAVE, xstate, lmask, hmask, err); + + /* We should never fault when copying to a kernel buffer: */ + WARN_ON_FPU(err); +@@ -277,22 +319,14 @@ static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate) + u64 mask = -1; + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + + WARN_ON(system_state != SYSTEM_BOOTING); + +- if (boot_cpu_has(X86_FEATURE_XSAVES)) +- asm volatile("1:"XRSTORS"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ if (static_cpu_has(X86_FEATURE_XSAVES)) ++ XSTATE_OP(XRSTORS, xstate, lmask, hmask, err); + else +- asm volatile("1:"XRSTOR"\n\t" +- "2:\n\t" +- xstate_fault(err) +- : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); ++ XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); + + /* We should never fault when copying from a kernel buffer: */ + WARN_ON_FPU(err); +@@ -306,33 +340,11 @@ static inline void copy_xregs_to_kernel(struct xregs_state *xstate) + u64 mask = -1; + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + + WARN_ON(!alternatives_patched); + +- /* +- * If xsaves is enabled, xsaves replaces xsaveopt because +- * it supports compact format and supervisor states in addition to +- * modified optimization in xsaveopt. +- * +- * Otherwise, if xsaveopt is enabled, xsaveopt replaces xsave +- * because xsaveopt supports modified optimization which is not +- * supported by xsave. +- * +- * If none of xsaves and xsaveopt is enabled, use xsave. +- */ +- alternative_input_2( +- "1:"XSAVE, +- XSAVEOPT, +- X86_FEATURE_XSAVEOPT, +- XSAVES, +- X86_FEATURE_XSAVES, +- [xstate] "D" (xstate), "a" (lmask), "d" (hmask) : +- "memory"); +- asm volatile("2:\n\t" +- xstate_fault(err) +- : "0" (err) +- : "memory"); ++ XSTATE_XSAVE(xstate, lmask, hmask, err); + + /* We should never fault when copying to a kernel buffer: */ + WARN_ON_FPU(err); +@@ -345,23 +357,9 @@ static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask) + { + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; ++ int err; + +- /* +- * Use xrstors to restore context if it is enabled. xrstors supports +- * compacted format of xsave area which is not supported by xrstor. +- */ +- alternative_input( +- "1: " XRSTOR, +- XRSTORS, +- X86_FEATURE_XSAVES, +- "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask) +- : "memory"); +- +- asm volatile("2:\n" +- xstate_fault(err) +- : "0" (err) +- : "memory"); ++ XSTATE_XRESTORE(xstate, lmask, hmask, err); + + /* We should never fault when copying from a kernel buffer: */ + WARN_ON_FPU(err); +@@ -389,12 +387,10 @@ static inline int copy_xregs_to_user(struct xregs_state __user *buf) + if (unlikely(err)) + return -EFAULT; + +- __asm__ __volatile__(ASM_STAC "\n" +- "1:"XSAVE"\n" +- "2: " ASM_CLAC "\n" +- xstate_fault(err) +- : "D" (buf), "a" (-1), "d" (-1), "0" (err) +- : "memory"); ++ stac(); ++ XSTATE_OP(XSAVE, buf, -1, -1, err); ++ clac(); ++ + return err; + } + +@@ -406,14 +402,12 @@ static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask) + struct xregs_state *xstate = ((__force struct xregs_state *)buf); + u32 lmask = mask; + u32 hmask = mask >> 32; +- int err = 0; +- +- __asm__ __volatile__(ASM_STAC "\n" +- "1:"XRSTOR"\n" +- "2: " ASM_CLAC "\n" +- xstate_fault(err) +- : "D" (xstate), "a" (lmask), "d" (hmask), "0" (err) +- : "memory"); /* memory required? */ ++ int err; ++ ++ stac(); ++ XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); ++ clac(); ++ + return err; + } + +@@ -467,7 +461,7 @@ static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate) + * pending. Clear the x87 state here by setting it to fixed values. + * "m" is a random variable that should be in L1. + */ +- if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { ++ if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) { + asm volatile( + "fnclex\n\t" + "emms\n\t" +diff --git a/arch/x86/include/asm/irq_work.h b/arch/x86/include/asm/irq_work.h +index 78162f8e248b..d0afb05c84fc 100644 +--- a/arch/x86/include/asm/irq_work.h ++++ b/arch/x86/include/asm/irq_work.h +@@ -1,7 +1,7 @@ + #ifndef _ASM_IRQ_WORK_H + #define _ASM_IRQ_WORK_H + +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + + static inline bool arch_irq_work_has_interrupt(void) + { +diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h +index c70689b5e5aa..0deeb2d26df7 100644 +--- a/arch/x86/include/asm/mwait.h ++++ b/arch/x86/include/asm/mwait.h +@@ -3,6 +3,8 @@ + + #include <linux/sched.h> + ++#include <asm/cpufeature.h> ++ + #define MWAIT_SUBSTATE_MASK 0xf + #define MWAIT_CSTATE_MASK 0xf + #define MWAIT_SUBSTATE_SIZE 4 +diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h +index 249f1c769f21..8b910416243c 100644 +--- a/arch/x86/include/asm/nospec-branch.h ++++ b/arch/x86/include/asm/nospec-branch.h +@@ -5,7 +5,7 @@ + + #include <asm/alternative.h> + #include <asm/alternative-asm.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + + /* + * Fill the CPU return stack buffer. +diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h +index 9e77cea2a8ef..8e415cf65457 100644 +--- a/arch/x86/include/asm/processor.h ++++ b/arch/x86/include/asm/processor.h +@@ -13,7 +13,7 @@ struct vm86; + #include <asm/types.h> + #include <uapi/asm/sigcontext.h> + #include <asm/current.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/page.h> + #include <asm/pgtable_types.h> + #include <asm/percpu.h> +@@ -24,7 +24,6 @@ struct vm86; + #include <asm/fpu/types.h> + + #include <linux/personality.h> +-#include <linux/cpumask.h> + #include <linux/cache.h> + #include <linux/threads.h> + #include <linux/math64.h> +diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h +index 5c6e4fb370f5..fac9a5c0abe9 100644 +--- a/arch/x86/include/asm/required-features.h ++++ b/arch/x86/include/asm/required-features.h +@@ -92,5 +92,14 @@ + #define REQUIRED_MASK7 0 + #define REQUIRED_MASK8 0 + #define REQUIRED_MASK9 0 ++#define REQUIRED_MASK10 0 ++#define REQUIRED_MASK11 0 ++#define REQUIRED_MASK12 0 ++#define REQUIRED_MASK13 0 ++#define REQUIRED_MASK14 0 ++#define REQUIRED_MASK15 0 ++#define REQUIRED_MASK16 0 ++#define REQUIRED_MASK17 0 ++#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) + + #endif /* _ASM_X86_REQUIRED_FEATURES_H */ +diff --git a/arch/x86/include/asm/smap.h b/arch/x86/include/asm/smap.h +index ba665ebd17bb..db333300bd4b 100644 +--- a/arch/x86/include/asm/smap.h ++++ b/arch/x86/include/asm/smap.h +@@ -15,7 +15,7 @@ + + #include <linux/stringify.h> + #include <asm/nops.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + + /* "Raw" instruction opcodes */ + #define __ASM_CLAC .byte 0x0f,0x01,0xca +diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h +index a438c5598a90..04d6eef5f8a5 100644 +--- a/arch/x86/include/asm/smp.h ++++ b/arch/x86/include/asm/smp.h +@@ -16,7 +16,6 @@ + #endif + #include <asm/thread_info.h> + #include <asm/cpumask.h> +-#include <asm/cpufeature.h> + + extern int smp_num_siblings; + extern unsigned int num_processors; +diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h +index 9b028204685d..18c9aaa8c043 100644 +--- a/arch/x86/include/asm/thread_info.h ++++ b/arch/x86/include/asm/thread_info.h +@@ -49,7 +49,7 @@ + */ + #ifndef __ASSEMBLY__ + struct task_struct; +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <linux/atomic.h> + + struct thread_info { +diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h +index a691b66cc40a..e2a89d2577fb 100644 +--- a/arch/x86/include/asm/tlbflush.h ++++ b/arch/x86/include/asm/tlbflush.h +@@ -5,6 +5,7 @@ + #include <linux/sched.h> + + #include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/special_insns.h> + #include <asm/smp.h> + +diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h +index f2f9b39b274a..d83a55b95a48 100644 +--- a/arch/x86/include/asm/uaccess_64.h ++++ b/arch/x86/include/asm/uaccess_64.h +@@ -8,7 +8,7 @@ + #include <linux/errno.h> + #include <linux/lockdep.h> + #include <asm/alternative.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/page.h> + + /* +diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c +index 2bd2292a316d..bac0805ea1d9 100644 +--- a/arch/x86/kernel/apic/apic_numachip.c ++++ b/arch/x86/kernel/apic/apic_numachip.c +@@ -30,7 +30,7 @@ static unsigned int numachip1_get_apic_id(unsigned long x) + unsigned long value; + unsigned int id = (x >> 24) & 0xff; + +- if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) { ++ if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { + rdmsrl(MSR_FAM10H_NODE_ID, value); + id |= (value << 2) & 0xff00; + } +@@ -178,7 +178,7 @@ static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) + this_cpu_write(cpu_llc_id, node); + + /* Account for nodes per socket in multi-core-module processors */ +- if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) { ++ if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { + rdmsrl(MSR_FAM10H_NODE_ID, val); + nodes = ((val >> 3) & 7) + 1; + } +diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile +index 8f184615053b..924b65794abd 100644 +--- a/arch/x86/kernel/cpu/Makefile ++++ b/arch/x86/kernel/cpu/Makefile +@@ -62,7 +62,7 @@ ifdef CONFIG_X86_FEATURE_NAMES + quiet_cmd_mkcapflags = MKCAP $@ + cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $< $@ + +-cpufeature = $(src)/../../include/asm/cpufeature.h ++cpufeature = $(src)/../../include/asm/cpufeatures.h + + targets += capflags.c + $(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE +diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c +index d8fba5c15fbd..6608c03c2126 100644 +--- a/arch/x86/kernel/cpu/centaur.c ++++ b/arch/x86/kernel/cpu/centaur.c +@@ -1,7 +1,7 @@ + #include <linux/bitops.h> + #include <linux/kernel.h> + +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/e820.h> + #include <asm/mtrr.h> + #include <asm/msr.h> +@@ -43,7 +43,7 @@ static void init_c3(struct cpuinfo_x86 *c) + /* store Centaur Extended Feature Flags as + * word 5 of the CPU capability bit array + */ +- c->x86_capability[5] = cpuid_edx(0xC0000001); ++ c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); + } + #ifdef CONFIG_X86_32 + /* Cyrix III family needs CX8 & PGE explicitly enabled. */ +diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c +index 0498ad3702f5..814276d0eed1 100644 +--- a/arch/x86/kernel/cpu/common.c ++++ b/arch/x86/kernel/cpu/common.c +@@ -676,50 +676,48 @@ static void apply_forced_caps(struct cpuinfo_x86 *c) + + void get_cpu_cap(struct cpuinfo_x86 *c) + { +- u32 tfms, xlvl; +- u32 ebx; ++ u32 eax, ebx, ecx, edx; + + /* Intel-defined flags: level 0x00000001 */ + if (c->cpuid_level >= 0x00000001) { +- u32 capability, excap; ++ cpuid(0x00000001, &eax, &ebx, &ecx, &edx); + +- cpuid(0x00000001, &tfms, &ebx, &excap, &capability); +- c->x86_capability[0] = capability; +- c->x86_capability[4] = excap; ++ c->x86_capability[CPUID_1_ECX] = ecx; ++ c->x86_capability[CPUID_1_EDX] = edx; + } + + /* Additional Intel-defined flags: level 0x00000007 */ + if (c->cpuid_level >= 0x00000007) { +- u32 eax, ebx, ecx, edx; +- + cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); + +- c->x86_capability[9] = ebx; ++ c->x86_capability[CPUID_7_0_EBX] = ebx; ++ ++ c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); ++ c->x86_capability[CPUID_7_ECX] = ecx; + } + + /* Extended state features: level 0x0000000d */ + if (c->cpuid_level >= 0x0000000d) { +- u32 eax, ebx, ecx, edx; +- + cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); + +- c->x86_capability[10] = eax; ++ c->x86_capability[CPUID_D_1_EAX] = eax; + } + + /* Additional Intel-defined flags: level 0x0000000F */ + if (c->cpuid_level >= 0x0000000F) { +- u32 eax, ebx, ecx, edx; + + /* QoS sub-leaf, EAX=0Fh, ECX=0 */ + cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); +- c->x86_capability[11] = edx; ++ c->x86_capability[CPUID_F_0_EDX] = edx; ++ + if (cpu_has(c, X86_FEATURE_CQM_LLC)) { + /* will be overridden if occupancy monitoring exists */ + c->x86_cache_max_rmid = ebx; + + /* QoS sub-leaf, EAX=0Fh, ECX=1 */ + cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); +- c->x86_capability[12] = edx; ++ c->x86_capability[CPUID_F_1_EDX] = edx; ++ + if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { + c->x86_cache_max_rmid = ecx; + c->x86_cache_occ_scale = ebx; +@@ -731,30 +729,39 @@ void get_cpu_cap(struct cpuinfo_x86 *c) + } + + /* AMD-defined flags: level 0x80000001 */ +- xlvl = cpuid_eax(0x80000000); +- c->extended_cpuid_level = xlvl; ++ eax = cpuid_eax(0x80000000); ++ c->extended_cpuid_level = eax; ++ ++ if ((eax & 0xffff0000) == 0x80000000) { ++ if (eax >= 0x80000001) { ++ cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + +- if ((xlvl & 0xffff0000) == 0x80000000) { +- if (xlvl >= 0x80000001) { +- c->x86_capability[1] = cpuid_edx(0x80000001); +- c->x86_capability[6] = cpuid_ecx(0x80000001); ++ c->x86_capability[CPUID_8000_0001_ECX] = ecx; ++ c->x86_capability[CPUID_8000_0001_EDX] = edx; + } + } + ++ if (c->extended_cpuid_level >= 0x80000007) { ++ cpuid(0x80000007, &eax, &ebx, &ecx, &edx); ++ ++ c->x86_capability[CPUID_8000_0007_EBX] = ebx; ++ c->x86_power = edx; ++ } ++ + if (c->extended_cpuid_level >= 0x80000008) { +- u32 eax = cpuid_eax(0x80000008); ++ cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + + c->x86_virt_bits = (eax >> 8) & 0xff; + c->x86_phys_bits = eax & 0xff; +- c->x86_capability[13] = cpuid_ebx(0x80000008); ++ c->x86_capability[CPUID_8000_0008_EBX] = ebx; + } + #ifdef CONFIG_X86_32 + else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) + c->x86_phys_bits = 36; + #endif + +- if (c->extended_cpuid_level >= 0x80000007) +- c->x86_power = cpuid_edx(0x80000007); ++ if (c->extended_cpuid_level >= 0x8000000a) ++ c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); + + init_scattered_cpuid_features(c); + } +@@ -1574,20 +1581,6 @@ void cpu_init(void) + } + #endif + +-#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS +-void warn_pre_alternatives(void) +-{ +- WARN(1, "You're using static_cpu_has before alternatives have run!\n"); +-} +-EXPORT_SYMBOL_GPL(warn_pre_alternatives); +-#endif +- +-inline bool __static_cpu_has_safe(u16 bit) +-{ +- return boot_cpu_has(bit); +-} +-EXPORT_SYMBOL_GPL(__static_cpu_has_safe); +- + static void bsp_resume(void) + { + if (this_cpu->c_bsp_resume) +diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c +index aaf152e79637..15e47c1cd412 100644 +--- a/arch/x86/kernel/cpu/cyrix.c ++++ b/arch/x86/kernel/cpu/cyrix.c +@@ -8,6 +8,7 @@ + #include <linux/timer.h> + #include <asm/pci-direct.h> + #include <asm/tsc.h> ++#include <asm/cpufeature.h> + + #include "cpu.h" + +diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c +index 565648bc1a0a..9299e3bdfad6 100644 +--- a/arch/x86/kernel/cpu/intel.c ++++ b/arch/x86/kernel/cpu/intel.c +@@ -8,7 +8,7 @@ + #include <linux/module.h> + #include <linux/uaccess.h> + +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/pgtable.h> + #include <asm/msr.h> + #include <asm/bugs.h> +diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c +index 3fa72317ad78..3557b3ceab14 100644 +--- a/arch/x86/kernel/cpu/intel_cacheinfo.c ++++ b/arch/x86/kernel/cpu/intel_cacheinfo.c +@@ -14,7 +14,7 @@ + #include <linux/sysfs.h> + #include <linux/pci.h> + +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/amd_nb.h> + #include <asm/smp.h> + +diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c +index afa9f0d487ea..fbb5e90557a5 100644 +--- a/arch/x86/kernel/cpu/match.c ++++ b/arch/x86/kernel/cpu/match.c +@@ -1,5 +1,5 @@ + #include <asm/cpu_device_id.h> +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <linux/cpu.h> + #include <linux/module.h> + #include <linux/slab.h> +diff --git a/arch/x86/kernel/cpu/mkcapflags.sh b/arch/x86/kernel/cpu/mkcapflags.sh +index 3f20710a5b23..6988c74409a8 100644 +--- a/arch/x86/kernel/cpu/mkcapflags.sh ++++ b/arch/x86/kernel/cpu/mkcapflags.sh +@@ -1,6 +1,6 @@ + #!/bin/sh + # +-# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeature.h ++# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeatures.h + # + + IN=$1 +@@ -49,8 +49,8 @@ dump_array() + trap 'rm "$OUT"' EXIT + + ( +- echo "#ifndef _ASM_X86_CPUFEATURE_H" +- echo "#include <asm/cpufeature.h>" ++ echo "#ifndef _ASM_X86_CPUFEATURES_H" ++ echo "#include <asm/cpufeatures.h>" + echo "#endif" + echo "" + +diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c +index f924f41af89a..49bd700d9b7f 100644 +--- a/arch/x86/kernel/cpu/mtrr/main.c ++++ b/arch/x86/kernel/cpu/mtrr/main.c +@@ -47,7 +47,7 @@ + #include <linux/smp.h> + #include <linux/syscore_ops.h> + +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/e820.h> + #include <asm/mtrr.h> + #include <asm/msr.h> +diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c +index 608fb26c7254..8cb57df9398d 100644 +--- a/arch/x86/kernel/cpu/scattered.c ++++ b/arch/x86/kernel/cpu/scattered.c +@@ -31,32 +31,12 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) + const struct cpuid_bit *cb; + + static const struct cpuid_bit cpuid_bits[] = { +- { X86_FEATURE_DTHERM, CR_EAX, 0, 0x00000006, 0 }, +- { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006, 0 }, +- { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006, 0 }, +- { X86_FEATURE_PLN, CR_EAX, 4, 0x00000006, 0 }, +- { X86_FEATURE_PTS, CR_EAX, 6, 0x00000006, 0 }, +- { X86_FEATURE_HWP, CR_EAX, 7, 0x00000006, 0 }, +- { X86_FEATURE_HWP_NOTIFY, CR_EAX, 8, 0x00000006, 0 }, +- { X86_FEATURE_HWP_ACT_WINDOW, CR_EAX, 9, 0x00000006, 0 }, +- { X86_FEATURE_HWP_EPP, CR_EAX,10, 0x00000006, 0 }, +- { X86_FEATURE_HWP_PKG_REQ, CR_EAX,11, 0x00000006, 0 }, + { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 }, + { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, + { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, + { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, + { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, + { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, +- { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 }, +- { X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 }, +- { X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a, 0 }, +- { X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a, 0 }, +- { X86_FEATURE_TSCRATEMSR, CR_EDX, 4, 0x8000000a, 0 }, +- { X86_FEATURE_VMCBCLEAN, CR_EDX, 5, 0x8000000a, 0 }, +- { X86_FEATURE_FLUSHBYASID, CR_EDX, 6, 0x8000000a, 0 }, +- { X86_FEATURE_DECODEASSISTS, CR_EDX, 7, 0x8000000a, 0 }, +- { X86_FEATURE_PAUSEFILTER, CR_EDX,10, 0x8000000a, 0 }, +- { X86_FEATURE_PFTHRESHOLD, CR_EDX,12, 0x8000000a, 0 }, + { 0, 0, 0, 0, 0 } + }; + +diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c +index 3fa0e5ad86b4..a19a663282b5 100644 +--- a/arch/x86/kernel/cpu/transmeta.c ++++ b/arch/x86/kernel/cpu/transmeta.c +@@ -1,6 +1,6 @@ + #include <linux/kernel.h> + #include <linux/mm.h> +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/msr.h> + #include "cpu.h" + +@@ -12,7 +12,7 @@ static void early_init_transmeta(struct cpuinfo_x86 *c) + xlvl = cpuid_eax(0x80860000); + if ((xlvl & 0xffff0000) == 0x80860000) { + if (xlvl >= 0x80860001) +- c->x86_capability[2] = cpuid_edx(0x80860001); ++ c->x86_capability[CPUID_8086_0001_EDX] = cpuid_edx(0x80860001); + } + } + +@@ -82,7 +82,7 @@ static void init_transmeta(struct cpuinfo_x86 *c) + /* Unhide possibly hidden capability flags */ + rdmsr(0x80860004, cap_mask, uk); + wrmsr(0x80860004, ~0, uk); +- c->x86_capability[0] = cpuid_edx(0x00000001); ++ c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001); + wrmsr(0x80860004, cap_mask, uk); + + /* All Transmeta CPUs have a constant TSC */ +diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c +index 52a2526c3fbe..19bc19d5e174 100644 +--- a/arch/x86/kernel/e820.c ++++ b/arch/x86/kernel/e820.c +@@ -24,6 +24,7 @@ + #include <asm/e820.h> + #include <asm/proto.h> + #include <asm/setup.h> ++#include <asm/cpufeature.h> + + /* + * The e820 map is the map that gets modified e.g. with command line parameters +diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S +index 70284d38fdc2..1c0b49fd6365 100644 +--- a/arch/x86/kernel/head_32.S ++++ b/arch/x86/kernel/head_32.S +@@ -19,7 +19,7 @@ + #include <asm/setup.h> + #include <asm/processor-flags.h> + #include <asm/msr-index.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/percpu.h> + #include <asm/nops.h> + #include <asm/bootparam.h> +diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S +index 4034e905741a..734ba1d0f686 100644 +--- a/arch/x86/kernel/head_64.S ++++ b/arch/x86/kernel/head_64.S +@@ -76,9 +76,7 @@ startup_64: + subq $_text - __START_KERNEL_map, %rbp + + /* Is the address not 2M aligned? */ +- movq %rbp, %rax +- andl $~PMD_PAGE_MASK, %eax +- testl %eax, %eax ++ testl $~PMD_PAGE_MASK, %ebp + jnz bad_address + + /* +diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c +index f48eb8eeefe2..3fdc1e53aaac 100644 +--- a/arch/x86/kernel/hpet.c ++++ b/arch/x86/kernel/hpet.c +@@ -12,6 +12,7 @@ + #include <linux/pm.h> + #include <linux/io.h> + ++#include <asm/cpufeature.h> + #include <asm/irqdomain.h> + #include <asm/fixmap.h> + #include <asm/hpet.h> +diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c +index 113e70784854..f95ac5d435aa 100644 +--- a/arch/x86/kernel/msr.c ++++ b/arch/x86/kernel/msr.c +@@ -40,7 +40,7 @@ + #include <linux/uaccess.h> + #include <linux/gfp.h> + +-#include <asm/processor.h> ++#include <asm/cpufeature.h> + #include <asm/msr.h> + + static struct class *msr_class; +diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c +index c6aace2bbe08..b8105289c60b 100644 +--- a/arch/x86/kernel/uprobes.c ++++ b/arch/x86/kernel/uprobes.c +@@ -290,7 +290,7 @@ static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool + insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64); + /* has the side-effect of processing the entire instruction */ + insn_get_length(insn); +- if (WARN_ON_ONCE(!insn_complete(insn))) ++ if (!insn_complete(insn)) + return -ENOEXEC; + + if (is_prefix_bad(insn)) +diff --git a/arch/x86/kernel/verify_cpu.S b/arch/x86/kernel/verify_cpu.S +index 4cf401f581e7..b7c9db5deebe 100644 +--- a/arch/x86/kernel/verify_cpu.S ++++ b/arch/x86/kernel/verify_cpu.S +@@ -30,7 +30,7 @@ + * appropriately. Either display a message or halt. + */ + +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/msr-index.h> + + verify_cpu: +diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c +index d6d64a519559..7f4839ef3608 100644 +--- a/arch/x86/kernel/vm86_32.c ++++ b/arch/x86/kernel/vm86_32.c +@@ -358,7 +358,7 @@ static long do_sys_vm86(struct vm86plus_struct __user *user_vm86, bool plus) + /* make room for real-mode segments */ + tsk->thread.sp0 += 16; + +- if (static_cpu_has_safe(X86_FEATURE_SEP)) ++ if (static_cpu_has(X86_FEATURE_SEP)) + tsk->thread.sysenter_cs = 0; + + load_sp0(tss, &tsk->thread); +diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S +index e065065a4dfb..a703842b54de 100644 +--- a/arch/x86/kernel/vmlinux.lds.S ++++ b/arch/x86/kernel/vmlinux.lds.S +@@ -202,6 +202,17 @@ SECTIONS + :init + #endif + ++ /* ++ * Section for code used exclusively before alternatives are run. All ++ * references to such code must be patched out by alternatives, normally ++ * by using X86_FEATURE_ALWAYS CPU feature bit. ++ * ++ * See static_cpu_has() for an example. ++ */ ++ .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) { ++ *(.altinstr_aux) ++ } ++ + INIT_DATA_SECTION(16) + + .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { +diff --git a/arch/x86/lib/clear_page_64.S b/arch/x86/lib/clear_page_64.S +index a2fe51b00cce..65be7cfaf947 100644 +--- a/arch/x86/lib/clear_page_64.S ++++ b/arch/x86/lib/clear_page_64.S +@@ -1,5 +1,5 @@ + #include <linux/linkage.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + + /* +diff --git a/arch/x86/lib/copy_page_64.S b/arch/x86/lib/copy_page_64.S +index 009f98216b7e..24ef1c2104d4 100644 +--- a/arch/x86/lib/copy_page_64.S ++++ b/arch/x86/lib/copy_page_64.S +@@ -1,7 +1,7 @@ + /* Written 2003 by Andi Kleen, based on a kernel by Evandro Menezes */ + + #include <linux/linkage.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + + /* +diff --git a/arch/x86/lib/copy_user_64.S b/arch/x86/lib/copy_user_64.S +index 423644c230e7..accf7f2f557f 100644 +--- a/arch/x86/lib/copy_user_64.S ++++ b/arch/x86/lib/copy_user_64.S +@@ -10,7 +10,7 @@ + #include <asm/current.h> + #include <asm/asm-offsets.h> + #include <asm/thread_info.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + #include <asm/asm.h> + #include <asm/smap.h> +diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S +index 16698bba87de..a0de849435ad 100644 +--- a/arch/x86/lib/memcpy_64.S ++++ b/arch/x86/lib/memcpy_64.S +@@ -1,7 +1,7 @@ + /* Copyright 2002 Andi Kleen */ + + #include <linux/linkage.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + + /* +diff --git a/arch/x86/lib/memmove_64.S b/arch/x86/lib/memmove_64.S +index ca2afdd6d98e..90ce01bee00c 100644 +--- a/arch/x86/lib/memmove_64.S ++++ b/arch/x86/lib/memmove_64.S +@@ -6,7 +6,7 @@ + * - Copyright 2011 Fenghua Yu <[email protected]> + */ + #include <linux/linkage.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + + #undef memmove +diff --git a/arch/x86/lib/memset_64.S b/arch/x86/lib/memset_64.S +index 2661fad05827..c9c81227ea37 100644 +--- a/arch/x86/lib/memset_64.S ++++ b/arch/x86/lib/memset_64.S +@@ -1,7 +1,7 @@ + /* Copyright 2002 Andi Kleen, SuSE Labs */ + + #include <linux/linkage.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + + .weak memset +diff --git a/arch/x86/lib/retpoline.S b/arch/x86/lib/retpoline.S +index 3d06b482ebc7..7bbb853e36bd 100644 +--- a/arch/x86/lib/retpoline.S ++++ b/arch/x86/lib/retpoline.S +@@ -3,7 +3,7 @@ + #include <linux/stringify.h> + #include <linux/linkage.h> + #include <asm/dwarf2.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/alternative-asm.h> + #include <asm-generic/export.h> + #include <asm/nospec-branch.h> +diff --git a/arch/x86/mm/setup_nx.c b/arch/x86/mm/setup_nx.c +index 92e2eacb3321..f65a33f505b6 100644 +--- a/arch/x86/mm/setup_nx.c ++++ b/arch/x86/mm/setup_nx.c +@@ -4,6 +4,7 @@ + + #include <asm/pgtable.h> + #include <asm/proto.h> ++#include <asm/cpufeature.h> + + static int disable_nx; + +diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c +index 50d86c0e9ba4..660a83c8287b 100644 +--- a/arch/x86/oprofile/op_model_amd.c ++++ b/arch/x86/oprofile/op_model_amd.c +@@ -24,7 +24,6 @@ + #include <asm/nmi.h> + #include <asm/apic.h> + #include <asm/processor.h> +-#include <asm/cpufeature.h> + + #include "op_x86_model.h" + #include "op_counter.h" +diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h +index 755481f14d90..764ac2fc53fe 100644 +--- a/arch/x86/um/asm/barrier.h ++++ b/arch/x86/um/asm/barrier.h +@@ -3,7 +3,7 @@ + + #include <asm/asm.h> + #include <asm/segment.h> +-#include <asm/cpufeature.h> ++#include <asm/cpufeatures.h> + #include <asm/cmpxchg.h> + #include <asm/nops.h> + +diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c +index 5a6a01135470..34fdaa6e99ba 100644 +--- a/drivers/ata/ahci.c ++++ b/drivers/ata/ahci.c +@@ -1229,6 +1229,59 @@ static bool ahci_broken_suspend(struct pci_dev *pdev) + return strcmp(buf, dmi->driver_data) < 0; + } + ++static bool ahci_broken_lpm(struct pci_dev *pdev) ++{ ++ static const struct dmi_system_id sysids[] = { ++ /* Various Lenovo 50 series have LPM issues with older BIOSen */ ++ { ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), ++ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), ++ }, ++ .driver_data = "20180406", /* 1.31 */ ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), ++ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), ++ }, ++ .driver_data = "20180420", /* 1.28 */ ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), ++ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), ++ }, ++ .driver_data = "20180315", /* 1.33 */ ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), ++ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), ++ }, ++ /* ++ * Note date based on release notes, 2.35 has been ++ * reported to be good, but I've been unable to get ++ * a hold of the reporter to get the DMI BIOS date. ++ * TODO: fix this. ++ */ ++ .driver_data = "20180310", /* 2.35 */ ++ }, ++ { } /* terminate list */ ++ }; ++ const struct dmi_system_id *dmi = dmi_first_match(sysids); ++ int year, month, date; ++ char buf[9]; ++ ++ if (!dmi) ++ return false; ++ ++ dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); ++ snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); ++ ++ return strcmp(buf, dmi->driver_data) < 0; ++} ++ + static bool ahci_broken_online(struct pci_dev *pdev) + { + #define ENCODE_BUSDEVFN(bus, slot, func) \ +@@ -1588,6 +1641,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) + "quirky BIOS, skipping spindown on poweroff\n"); + } + ++ if (ahci_broken_lpm(pdev)) { ++ pi.flags |= ATA_FLAG_NO_LPM; ++ dev_warn(&pdev->dev, ++ "BIOS update required for Link Power Management support\n"); ++ } ++ + if (ahci_broken_suspend(pdev)) { + hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; + dev_warn(&pdev->dev, +diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c +index 9afd06ee5b30..ba514fa733de 100644 +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -2209,6 +2209,9 @@ int ata_dev_configure(struct ata_device *dev) + (id[ATA_ID_SATA_CAPABILITY] & 0xe) == 0x2) + dev->horkage |= ATA_HORKAGE_NOLPM; + ++ if (ap->flags & ATA_FLAG_NO_LPM) ++ dev->horkage |= ATA_HORKAGE_NOLPM; ++ + if (dev->horkage & ATA_HORKAGE_NOLPM) { + ata_dev_warn(dev, "LPM support broken, forcing max_power\n"); + dev->link->ap->target_lpm_policy = ATA_LPM_MAX_POWER; +diff --git a/drivers/block/loop.c b/drivers/block/loop.c +index e8165ec55e6f..da3902ac16c8 100644 +--- a/drivers/block/loop.c ++++ b/drivers/block/loop.c +@@ -651,6 +651,36 @@ static void loop_reread_partitions(struct loop_device *lo, + __func__, lo->lo_number, lo->lo_file_name, rc); + } + ++static inline int is_loop_device(struct file *file) ++{ ++ struct inode *i = file->f_mapping->host; ++ ++ return i && S_ISBLK(i->i_mode) && MAJOR(i->i_rdev) == LOOP_MAJOR; ++} ++ ++static int loop_validate_file(struct file *file, struct block_device *bdev) ++{ ++ struct inode *inode = file->f_mapping->host; ++ struct file *f = file; ++ ++ /* Avoid recursion */ ++ while (is_loop_device(f)) { ++ struct loop_device *l; ++ ++ if (f->f_mapping->host->i_bdev == bdev) ++ return -EBADF; ++ ++ l = f->f_mapping->host->i_bdev->bd_disk->private_data; ++ if (l->lo_state == Lo_unbound) { ++ return -EINVAL; ++ } ++ f = l->lo_backing_file; ++ } ++ if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode)) ++ return -EINVAL; ++ return 0; ++} ++ + /* + * loop_change_fd switched the backing store of a loopback device to + * a new file. This is useful for operating system installers to free up +@@ -680,14 +710,15 @@ static int loop_change_fd(struct loop_device *lo, struct block_device *bdev, + if (!file) + goto out; + ++ error = loop_validate_file(file, bdev); ++ if (error) ++ goto out_putf; ++ + inode = file->f_mapping->host; + old_file = lo->lo_backing_file; + + error = -EINVAL; + +- if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode)) +- goto out_putf; +- + /* size of the new backing store needs to be the same */ + if (get_loop_size(lo, file) != get_loop_size(lo, old_file)) + goto out_putf; +@@ -708,13 +739,6 @@ static int loop_change_fd(struct loop_device *lo, struct block_device *bdev, + return error; + } + +-static inline int is_loop_device(struct file *file) +-{ +- struct inode *i = file->f_mapping->host; +- +- return i && S_ISBLK(i->i_mode) && MAJOR(i->i_rdev) == LOOP_MAJOR; +-} +- + /* loop sysfs attributes */ + + static ssize_t loop_attr_show(struct device *dev, char *page, +@@ -811,16 +835,17 @@ static struct attribute_group loop_attribute_group = { + .attrs= loop_attrs, + }; + +-static int loop_sysfs_init(struct loop_device *lo) ++static void loop_sysfs_init(struct loop_device *lo) + { +- return sysfs_create_group(&disk_to_dev(lo->lo_disk)->kobj, +- &loop_attribute_group); ++ lo->sysfs_inited = !sysfs_create_group(&disk_to_dev(lo->lo_disk)->kobj, ++ &loop_attribute_group); + } + + static void loop_sysfs_exit(struct loop_device *lo) + { +- sysfs_remove_group(&disk_to_dev(lo->lo_disk)->kobj, +- &loop_attribute_group); ++ if (lo->sysfs_inited) ++ sysfs_remove_group(&disk_to_dev(lo->lo_disk)->kobj, ++ &loop_attribute_group); + } + + static void loop_config_discard(struct loop_device *lo) +@@ -872,7 +897,7 @@ static int loop_prepare_queue(struct loop_device *lo) + static int loop_set_fd(struct loop_device *lo, fmode_t mode, + struct block_device *bdev, unsigned int arg) + { +- struct file *file, *f; ++ struct file *file; + struct inode *inode; + struct address_space *mapping; + unsigned lo_blocksize; +@@ -892,29 +917,13 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode, + if (lo->lo_state != Lo_unbound) + goto out_putf; + +- /* Avoid recursion */ +- f = file; +- while (is_loop_device(f)) { +- struct loop_device *l; +- +- if (f->f_mapping->host->i_bdev == bdev) +- goto out_putf; +- +- l = f->f_mapping->host->i_bdev->bd_disk->private_data; +- if (l->lo_state == Lo_unbound) { +- error = -EINVAL; +- goto out_putf; +- } +- f = l->lo_backing_file; +- } ++ error = loop_validate_file(file, bdev); ++ if (error) ++ goto out_putf; + + mapping = file->f_mapping; + inode = mapping->host; + +- error = -EINVAL; +- if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode)) +- goto out_putf; +- + if (!(file->f_mode & FMODE_WRITE) || !(mode & FMODE_WRITE) || + !file->f_op->write_iter) + lo_flags |= LO_FLAGS_READ_ONLY; +diff --git a/drivers/block/loop.h b/drivers/block/loop.h +index fb2237c73e61..60f0fd2c0c65 100644 +--- a/drivers/block/loop.h ++++ b/drivers/block/loop.h +@@ -59,6 +59,7 @@ struct loop_device { + struct kthread_worker worker; + struct task_struct *worker_task; + bool use_dio; ++ bool sysfs_inited; + + struct request_queue *lo_queue; + struct blk_mq_tag_set tag_set; +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index b316ab7e8996..60e2c9faa95f 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -512,6 +512,9 @@ + #define USB_VENDOR_ID_IRTOUCHSYSTEMS 0x6615 + #define USB_DEVICE_ID_IRTOUCH_INFRARED_USB 0x0070 + ++#define USB_VENDOR_ID_INNOMEDIA 0x1292 ++#define USB_DEVICE_ID_INNEX_GENESIS_ATARI 0x4745 ++ + #define USB_VENDOR_ID_ITE 0x048d + #define USB_DEVICE_ID_ITE_LENOVO_YOGA 0x8386 + #define USB_DEVICE_ID_ITE_LENOVO_YOGA2 0x8350 +diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c +index ce1543d69acb..c9a11315493b 100644 +--- a/drivers/hid/usbhid/hid-quirks.c ++++ b/drivers/hid/usbhid/hid-quirks.c +@@ -152,6 +152,7 @@ static const struct hid_blacklist { + { USB_VENDOR_ID_MULTIPLE_1781, USB_DEVICE_ID_RAPHNET_4NES4SNES_OLD, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_DRACAL_RAPHNET, USB_DEVICE_ID_RAPHNET_2NES2SNES, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_DRACAL_RAPHNET, USB_DEVICE_ID_RAPHNET_4NES4SNES, HID_QUIRK_MULTI_INPUT }, ++ { USB_VENDOR_ID_INNOMEDIA, USB_DEVICE_ID_INNEX_GENESIS_ATARI, HID_QUIRK_MULTI_INPUT }, + + { 0, 0 } + }; +diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig +index aa26f3c3416b..c151bb625179 100644 +--- a/drivers/infiniband/Kconfig ++++ b/drivers/infiniband/Kconfig +@@ -33,6 +33,18 @@ config INFINIBAND_USER_ACCESS + libibverbs, libibcm and a hardware driver library from + <http://www.openfabrics.org/git/>. + ++config INFINIBAND_USER_ACCESS_UCM ++ bool "Userspace CM (UCM, DEPRECATED)" ++ depends on BROKEN ++ depends on INFINIBAND_USER_ACCESS ++ help ++ The UCM module has known security flaws, which no one is ++ interested to fix. The user-space part of this code was ++ dropped from the upstream a long time ago. ++ ++ This option is DEPRECATED and planned to be removed. ++ ++ + config INFINIBAND_USER_MEM + bool + depends on INFINIBAND_USER_ACCESS != n +diff --git a/drivers/infiniband/core/Makefile b/drivers/infiniband/core/Makefile +index d43a8994ac5c..737612a442be 100644 +--- a/drivers/infiniband/core/Makefile ++++ b/drivers/infiniband/core/Makefile +@@ -5,8 +5,8 @@ obj-$(CONFIG_INFINIBAND) += ib_core.o ib_mad.o ib_sa.o \ + ib_cm.o iw_cm.o ib_addr.o \ + $(infiniband-y) + obj-$(CONFIG_INFINIBAND_USER_MAD) += ib_umad.o +-obj-$(CONFIG_INFINIBAND_USER_ACCESS) += ib_uverbs.o ib_ucm.o \ +- $(user_access-y) ++obj-$(CONFIG_INFINIBAND_USER_ACCESS) += ib_uverbs.o $(user_access-y) ++obj-$(CONFIG_INFINIBAND_USER_ACCESS_UCM) += ib_ucm.o $(user_access-y) + + ib_core-y := packer.o ud_header.o verbs.o sysfs.o \ + device.o fmr_pool.o cache.o netlink.o \ +diff --git a/drivers/infiniband/hw/cxgb4/mem.c b/drivers/infiniband/hw/cxgb4/mem.c +index e1629ab58db7..8218d714fa01 100644 +--- a/drivers/infiniband/hw/cxgb4/mem.c ++++ b/drivers/infiniband/hw/cxgb4/mem.c +@@ -926,7 +926,7 @@ static int c4iw_set_page(struct ib_mr *ibmr, u64 addr) + { + struct c4iw_mr *mhp = to_c4iw_mr(ibmr); + +- if (unlikely(mhp->mpl_len == mhp->max_mpl_len)) ++ if (unlikely(mhp->mpl_len == mhp->attr.pbl_size)) + return -ENOMEM; + + mhp->mpl[mhp->mpl_len++] = addr; +diff --git a/drivers/misc/ibmasm/ibmasmfs.c b/drivers/misc/ibmasm/ibmasmfs.c +index e8b933111e0d..92109cadc3fc 100644 +--- a/drivers/misc/ibmasm/ibmasmfs.c ++++ b/drivers/misc/ibmasm/ibmasmfs.c +@@ -507,35 +507,14 @@ static int remote_settings_file_close(struct inode *inode, struct file *file) + static ssize_t remote_settings_file_read(struct file *file, char __user *buf, size_t count, loff_t *offset) + { + void __iomem *address = (void __iomem *)file->private_data; +- unsigned char *page; +- int retval; + int len = 0; + unsigned int value; +- +- if (*offset < 0) +- return -EINVAL; +- if (count == 0 || count > 1024) +- return 0; +- if (*offset != 0) +- return 0; +- +- page = (unsigned char *)__get_free_page(GFP_KERNEL); +- if (!page) +- return -ENOMEM; ++ char lbuf[20]; + + value = readl(address); +- len = sprintf(page, "%d\n", value); +- +- if (copy_to_user(buf, page, len)) { +- retval = -EFAULT; +- goto exit; +- } +- *offset += len; +- retval = len; ++ len = snprintf(lbuf, sizeof(lbuf), "%d\n", value); + +-exit: +- free_page((unsigned long)page); +- return retval; ++ return simple_read_from_buffer(buf, count, offset, lbuf, len); + } + + static ssize_t remote_settings_file_write(struct file *file, const char __user *ubuff, size_t count, loff_t *offset) +diff --git a/drivers/misc/vmw_balloon.c b/drivers/misc/vmw_balloon.c +index fe90b7e04427..5e047bfc0cc4 100644 +--- a/drivers/misc/vmw_balloon.c ++++ b/drivers/misc/vmw_balloon.c +@@ -467,7 +467,7 @@ static int vmballoon_send_batched_lock(struct vmballoon *b, + unsigned int num_pages, bool is_2m_pages, unsigned int *target) + { + unsigned long status; +- unsigned long pfn = page_to_pfn(b->page); ++ unsigned long pfn = PHYS_PFN(virt_to_phys(b->batch_page)); + + STATS_INC(b->stats.lock[is_2m_pages]); + +@@ -515,7 +515,7 @@ static bool vmballoon_send_batched_unlock(struct vmballoon *b, + unsigned int num_pages, bool is_2m_pages, unsigned int *target) + { + unsigned long status; +- unsigned long pfn = page_to_pfn(b->page); ++ unsigned long pfn = PHYS_PFN(virt_to_phys(b->batch_page)); + + STATS_INC(b->stats.unlock[is_2m_pages]); + +diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c +index 40ce175655e6..99f67764765f 100644 +--- a/drivers/usb/core/quirks.c ++++ b/drivers/usb/core/quirks.c +@@ -231,6 +231,10 @@ static const struct usb_device_id usb_quirk_list[] = { + /* Corsair K70 RGB */ + { USB_DEVICE(0x1b1c, 0x1b13), .driver_info = USB_QUIRK_DELAY_INIT }, + ++ /* Corsair Strafe */ ++ { USB_DEVICE(0x1b1c, 0x1b15), .driver_info = USB_QUIRK_DELAY_INIT | ++ USB_QUIRK_DELAY_CTRL_MSG }, ++ + /* Corsair Strafe RGB */ + { USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT | + USB_QUIRK_DELAY_CTRL_MSG }, +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index e4cf3322bcb3..0ec809a35a3f 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -638,7 +638,7 @@ struct xhci_ring *xhci_stream_id_to_ring( + if (!ep->stream_info) + return NULL; + +- if (stream_id > ep->stream_info->num_streams) ++ if (stream_id >= ep->stream_info->num_streams) + return NULL; + return ep->stream_info->stream_rings[stream_id]; + } +diff --git a/drivers/usb/misc/yurex.c b/drivers/usb/misc/yurex.c +index 343fa6ff9f4b..512c84adcace 100644 +--- a/drivers/usb/misc/yurex.c ++++ b/drivers/usb/misc/yurex.c +@@ -414,8 +414,7 @@ static ssize_t yurex_read(struct file *file, char __user *buffer, size_t count, + loff_t *ppos) + { + struct usb_yurex *dev; +- int retval = 0; +- int bytes_read = 0; ++ int len = 0; + char in_buffer[20]; + unsigned long flags; + +@@ -423,26 +422,16 @@ static ssize_t yurex_read(struct file *file, char __user *buffer, size_t count, + + mutex_lock(&dev->io_mutex); + if (!dev->interface) { /* already disconnected */ +- retval = -ENODEV; +- goto exit; ++ mutex_unlock(&dev->io_mutex); ++ return -ENODEV; + } + + spin_lock_irqsave(&dev->lock, flags); +- bytes_read = snprintf(in_buffer, 20, "%lld\n", dev->bbu); ++ len = snprintf(in_buffer, 20, "%lld\n", dev->bbu); + spin_unlock_irqrestore(&dev->lock, flags); +- +- if (*ppos < bytes_read) { +- if (copy_to_user(buffer, in_buffer + *ppos, bytes_read - *ppos)) +- retval = -EFAULT; +- else { +- retval = bytes_read - *ppos; +- *ppos += bytes_read; +- } +- } +- +-exit: + mutex_unlock(&dev->io_mutex); +- return retval; ++ ++ return simple_read_from_buffer(buffer, count, ppos, in_buffer, len); + } + + static ssize_t yurex_write(struct file *file, const char __user *user_buffer, +diff --git a/drivers/usb/serial/ch341.c b/drivers/usb/serial/ch341.c +index 71133d96f97d..f73ea14e8173 100644 +--- a/drivers/usb/serial/ch341.c ++++ b/drivers/usb/serial/ch341.c +@@ -118,7 +118,7 @@ static int ch341_control_in(struct usb_device *dev, + r = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), request, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, + value, index, buf, bufsize, DEFAULT_TIMEOUT); +- if (r < bufsize) { ++ if (r < (int)bufsize) { + if (r >= 0) { + dev_err(&dev->dev, + "short control message received (%d < %u)\n", +diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c +index 73835027a7cc..97382301c393 100644 +--- a/drivers/usb/serial/cp210x.c ++++ b/drivers/usb/serial/cp210x.c +@@ -145,6 +145,7 @@ static const struct usb_device_id id_table[] = { + { USB_DEVICE(0x10C4, 0x8977) }, /* CEL MeshWorks DevKit Device */ + { USB_DEVICE(0x10C4, 0x8998) }, /* KCF Technologies PRN */ + { USB_DEVICE(0x10C4, 0x89A4) }, /* CESINEL FTBC Flexible Thyristor Bridge Controller */ ++ { USB_DEVICE(0x10C4, 0x89FB) }, /* Qivicon ZigBee USB Radio Stick */ + { USB_DEVICE(0x10C4, 0x8A2A) }, /* HubZ dual ZigBee and Z-Wave dongle */ + { USB_DEVICE(0x10C4, 0x8A5E) }, /* CEL EM3588 ZigBee USB Stick Long Range */ + { USB_DEVICE(0x10C4, 0x8B34) }, /* Qivicon ZigBee USB Radio Stick */ +diff --git a/drivers/usb/serial/keyspan_pda.c b/drivers/usb/serial/keyspan_pda.c +index 6b0942428917..8a4047de43dc 100644 +--- a/drivers/usb/serial/keyspan_pda.c ++++ b/drivers/usb/serial/keyspan_pda.c +@@ -373,8 +373,10 @@ static int keyspan_pda_get_modem_info(struct usb_serial *serial, + 3, /* get pins */ + USB_TYPE_VENDOR|USB_RECIP_INTERFACE|USB_DIR_IN, + 0, 0, data, 1, 2000); +- if (rc >= 0) ++ if (rc == 1) + *value = *data; ++ else if (rc >= 0) ++ rc = -EIO; + + kfree(data); + return rc; +diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c +index ed883a7ad533..58ba6904a087 100644 +--- a/drivers/usb/serial/mos7840.c ++++ b/drivers/usb/serial/mos7840.c +@@ -482,6 +482,9 @@ static void mos7840_control_callback(struct urb *urb) + } + + dev_dbg(dev, "%s urb buffer size is %d\n", __func__, urb->actual_length); ++ if (urb->actual_length < 1) ++ goto out; ++ + dev_dbg(dev, "%s mos7840_port->MsrLsr is %d port %d\n", __func__, + mos7840_port->MsrLsr, mos7840_port->port_num); + data = urb->transfer_buffer; +diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c +index 7efd70bfeaf7..d106b981d86f 100644 +--- a/fs/btrfs/disk-io.c ++++ b/fs/btrfs/disk-io.c +@@ -923,7 +923,7 @@ static int check_async_write(struct inode *inode, unsigned long bio_flags) + if (bio_flags & EXTENT_BIO_TREE_LOG) + return 0; + #ifdef CONFIG_X86 +- if (static_cpu_has_safe(X86_FEATURE_XMM4_2)) ++ if (static_cpu_has(X86_FEATURE_XMM4_2)) + return 0; + #endif + return 1; +diff --git a/fs/inode.c b/fs/inode.c +index b95615f3fc50..a39c2724d8a0 100644 +--- a/fs/inode.c ++++ b/fs/inode.c +@@ -1937,8 +1937,14 @@ void inode_init_owner(struct inode *inode, const struct inode *dir, + inode->i_uid = current_fsuid(); + if (dir && dir->i_mode & S_ISGID) { + inode->i_gid = dir->i_gid; ++ ++ /* Directories are special, and always inherit S_ISGID */ + if (S_ISDIR(mode)) + mode |= S_ISGID; ++ else if ((mode & (S_ISGID | S_IXGRP)) == (S_ISGID | S_IXGRP) && ++ !in_group_p(inode->i_gid) && ++ !capable_wrt_inode_uidgid(dir, CAP_FSETID)) ++ mode &= ~S_ISGID; + } else + inode->i_gid = current_fsgid(); + inode->i_mode = mode; +diff --git a/include/linux/libata.h b/include/linux/libata.h +index b20a2752f934..6428ac4746de 100644 +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -210,6 +210,7 @@ enum { + ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */ + /* (doesn't imply presence) */ + ATA_FLAG_SATA = (1 << 1), ++ ATA_FLAG_NO_LPM = (1 << 2), /* host not happy with LPM */ + ATA_FLAG_NO_LOG_PAGE = (1 << 5), /* do not issue log page read */ + ATA_FLAG_NO_ATAPI = (1 << 6), /* No ATAPI support */ + ATA_FLAG_PIO_DMA = (1 << 7), /* PIO cmds via DMA */ +diff --git a/kernel/power/user.c b/kernel/power/user.c +index 526e8911460a..f83c1876b39c 100644 +--- a/kernel/power/user.c ++++ b/kernel/power/user.c +@@ -184,6 +184,11 @@ static ssize_t snapshot_write(struct file *filp, const char __user *buf, + res = PAGE_SIZE - pg_offp; + } + ++ if (!data_of(data->handle)) { ++ res = -EINVAL; ++ goto unlock; ++ } ++ + res = simple_write_to_buffer(data_of(data->handle), res, &pg_offp, + buf, count); + if (res > 0) +diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c +index 83c33a5bcffb..de67fea3cf46 100644 +--- a/lib/atomic64_test.c ++++ b/lib/atomic64_test.c +@@ -16,6 +16,10 @@ + #include <linux/kernel.h> + #include <linux/atomic.h> + ++#ifdef CONFIG_X86 ++#include <asm/cpufeature.h> /* for boot_cpu_has below */ ++#endif ++ + #define TEST(bit, op, c_op, val) \ + do { \ + atomic##bit##_set(&v, v0); \ +diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c +index 9f70c267a7a5..665fd87cc105 100644 +--- a/net/bridge/netfilter/ebtables.c ++++ b/net/bridge/netfilter/ebtables.c +@@ -701,6 +701,8 @@ ebt_check_entry(struct ebt_entry *e, struct net *net, + } + i = 0; + ++ memset(&mtpar, 0, sizeof(mtpar)); ++ memset(&tgpar, 0, sizeof(tgpar)); + mtpar.net = tgpar.net = net; + mtpar.table = tgpar.table = name; + mtpar.entryinfo = tgpar.entryinfo = e; +diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c +index dac62b5e7fe3..9363c1a70f16 100644 +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -663,6 +663,7 @@ find_check_entry(struct ipt_entry *e, struct net *net, const char *name, + return -ENOMEM; + + j = 0; ++ memset(&mtpar, 0, sizeof(mtpar)); + mtpar.net = net; + mtpar.table = name; + mtpar.entryinfo = &e->ip; +diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c +index 795c343347ec..6cb9e35d23ac 100644 +--- a/net/ipv6/netfilter/ip6_tables.c ++++ b/net/ipv6/netfilter/ip6_tables.c +@@ -676,6 +676,7 @@ find_check_entry(struct ip6t_entry *e, struct net *net, const char *name, + return -ENOMEM; + + j = 0; ++ memset(&mtpar, 0, sizeof(mtpar)); + mtpar.net = net; + mtpar.table = name; + mtpar.entryinfo = &e->ipv6; +diff --git a/net/netfilter/nfnetlink_queue.c b/net/netfilter/nfnetlink_queue.c +index 7edcfda288c4..54cde78c2718 100644 +--- a/net/netfilter/nfnetlink_queue.c ++++ b/net/netfilter/nfnetlink_queue.c +@@ -1106,6 +1106,9 @@ nfqnl_recv_unsupp(struct sock *ctnl, struct sk_buff *skb, + static const struct nla_policy nfqa_cfg_policy[NFQA_CFG_MAX+1] = { + [NFQA_CFG_CMD] = { .len = sizeof(struct nfqnl_msg_config_cmd) }, + [NFQA_CFG_PARAMS] = { .len = sizeof(struct nfqnl_msg_config_params) }, ++ [NFQA_CFG_QUEUE_MAXLEN] = { .type = NLA_U32 }, ++ [NFQA_CFG_MASK] = { .type = NLA_U32 }, ++ [NFQA_CFG_FLAGS] = { .type = NLA_U32 }, + }; + + static const struct nf_queue_handler nfqh = { +diff --git a/tools/build/Build.include b/tools/build/Build.include +index 4d000bc959b4..1c570528baf7 100644 +--- a/tools/build/Build.include ++++ b/tools/build/Build.include +@@ -62,8 +62,8 @@ dep-cmd = $(if $(wildcard $(fixdep)), + $(fixdep) $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp; \ + rm -f $(depfile); \ + mv -f $(dot-target).tmp $(dot-target).cmd, \ +- printf '\# cannot find fixdep (%s)\n' $(fixdep) > $(dot-target).cmd; \ +- printf '\# using basic dep data\n\n' >> $(dot-target).cmd; \ ++ printf '$(pound) cannot find fixdep (%s)\n' $(fixdep) > $(dot-target).cmd; \ ++ printf '$(pound) using basic dep data\n\n' >> $(dot-target).cmd; \ + cat $(depfile) >> $(dot-target).cmd; \ + printf '%s\n' 'cmd_$@ := $(make-cmd)' >> $(dot-target).cmd) +
