commit: 52309bfac338ac9104b5972d499ad185c1dee2a5 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Sun Apr 18 22:22:32 2021 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Sun Apr 18 22:22:32 2021 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=52309bfa
CPU Opt patch upd (includes rocket lake), BMQ rev 3 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> 0000_README | 2 +- 5013_enable-cpu-optimizations-for-gcc10.patch | 271 ++++++++++++++------- ...=> 5020_BMQ-and-PDS-io-scheduler-v5.11-r3.patch | 51 ++-- 3 files changed, 221 insertions(+), 103 deletions(-) diff --git a/0000_README b/0000_README index fa29041..09827cb 100644 --- a/0000_README +++ b/0000_README @@ -131,7 +131,7 @@ Patch: 5013_enable-cpu-optimizations-for-gcc10.patch From: https://github.com/graysky2/kernel_gcc_patch/ Desc: Kernel patch enables gcc = v10.1+ optimizations for additional CPUs. -Patch: 5020_BMQ-and-PDS-io-scheduler-v5.11-r2.patch +Patch: 5020_BMQ-and-PDS-io-scheduler-v5.11-r3.patch From: https://gitlab.com/alfredchen/linux-prjc Desc: BMQ(BitMap Queue) Scheduler. A new CPU scheduler developed from PDS(incld). Inspired by the scheduler in zircon. diff --git a/5013_enable-cpu-optimizations-for-gcc10.patch b/5013_enable-cpu-optimizations-for-gcc10.patch index c90b586..1868f23 100644 --- a/5013_enable-cpu-optimizations-for-gcc10.patch +++ b/5013_enable-cpu-optimizations-for-gcc10.patch @@ -1,64 +1,82 @@ -From 4666424a864159b4de572c90adb2c3e1fcdd5890 Mon Sep 17 00:00:00 2001 +From 59db769ad69e080c512b3890e1d27d6120f4a1a4 Mon Sep 17 00:00:00 2001 From: graysky <gray...@archlinux.us> -Date: Fri, 13 Nov 2020 15:45:08 -0500 -Subject: [PATCH]more-uarches-for-gcc-v10-and-kernel-5.8+ +Date: Mon, 12 Apr 2021 07:09:27 -0400 +Subject: [PATCH] more uarches for kernel 5.8+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit WARNING -This patch works with gcc versions 10.1+ and with kernel version 5.8+ and should +This patch works with all gcc versions 9.0+ and with kernel version 5.8+ and should NOT be applied when compiling on older versions of gcc due to key name changes of the march flags introduced with the version 4.9 release of gcc.[1] -Use the older version of this patch hosted on the same github for older -versions of gcc. - FEATURES This patch adds additional CPU options to the Linux kernel accessible under: Processor type and features ---> Processor family ---> -The expanded microarchitectures include: -* AMD Improved K8-family -* AMD K10-family -* AMD Family 10h (Barcelona) -* AMD Family 14h (Bobcat) -* AMD Family 16h (Jaguar) -* AMD Family 15h (Bulldozer) -* AMD Family 15h (Piledriver) -* AMD Family 15h (Steamroller) -* AMD Family 15h (Excavator) -* AMD Family 17h (Zen) -* AMD Family 17h (Zen 2) -* Intel Silvermont low-power processors -* Intel Goldmont low-power processors (Apollo Lake and Denverton) -* Intel Goldmont Plus low-power processors (Gemini Lake) -* Intel 1st Gen Core i3/i5/i7 (Nehalem) -* Intel 1.5 Gen Core i3/i5/i7 (Westmere) -* Intel 2nd Gen Core i3/i5/i7 (Sandybridge) -* Intel 3rd Gen Core i3/i5/i7 (Ivybridge) -* Intel 4th Gen Core i3/i5/i7 (Haswell) -* Intel 5th Gen Core i3/i5/i7 (Broadwell) -* Intel 6th Gen Core i3/i5/i7 (Skylake) -* Intel 6th Gen Core i7/i9 (Skylake X) -* Intel 8th Gen Core i3/i5/i7 (Cannon Lake) -* Intel 10th Gen Core i7/i9 (Ice Lake) -* Intel Xeon (Cascade Lake) -* Intel Xeon (Cooper Lake) -* Intel 3rd Gen 10nm++ i3/i5/i7/i9-family (Tiger Lake) +With the release of gcc 11.0, several generic 64-bit levels are offered which +are good for supported Intel or AMD CPUs: +• x86-64-v2 +• x86-64-v3 +• x86-64-v4 + +Users of glibc 2.33 and above can see which level is supported by current +hardware by running: + /lib/ld-linux-x86-64.so.2 --help | grep supported + +Alternatively, compare the flags from /proc/cpuinfo to this list.[2] + +CPU-specific microarchitectures include: +• AMD Improved K8-family +• AMD K10-family +• AMD Family 10h (Barcelona) +• AMD Family 14h (Bobcat) +• AMD Family 16h (Jaguar) +• AMD Family 15h (Bulldozer) +• AMD Family 15h (Piledriver) +• AMD Family 15h (Steamroller) +• AMD Family 15h (Excavator) +• AMD Family 17h (Zen) +• AMD Family 17h (Zen 2) +• AMD Family 19h (Zen 3)† +• Intel Silvermont low-power processors +• Intel Goldmont low-power processors (Apollo Lake and Denverton) +• Intel Goldmont Plus low-power processors (Gemini Lake) +• Intel 1st Gen Core i3/i5/i7 (Nehalem) +• Intel 1.5 Gen Core i3/i5/i7 (Westmere) +• Intel 2nd Gen Core i3/i5/i7 (Sandybridge) +• Intel 3rd Gen Core i3/i5/i7 (Ivybridge) +• Intel 4th Gen Core i3/i5/i7 (Haswell) +• Intel 5th Gen Core i3/i5/i7 (Broadwell) +• Intel 6th Gen Core i3/i5/i7 (Skylake) +• Intel 6th Gen Core i7/i9 (Skylake X) +• Intel 8th Gen Core i3/i5/i7 (Cannon Lake) +• Intel 10th Gen Core i7/i9 (Ice Lake) +• Intel Xeon (Cascade Lake) +• Intel Xeon (Cooper Lake)* +• Intel 3rd Gen 10nm++ i3/i5/i7/i9-family (Tiger Lake)* +• Intel 3rd Gen 10nm++ Xeon (Sapphire Rapids)‡ +• Intel 11th Gen i3/i5/i7/i9-family (Rocket Lake)‡ +• Intel 12th Gen i3/i5/i7/i9-family (Alder Lake)‡ + +Notes: If not otherwise noted, gcc >=9.1 is required for support. + *Requires gcc >=10.1 †Required gcc >=10.3 ‡Required gcc >=11.0 It also offers to compile passing the 'native' option which, "selects the CPU to generate code for at compilation time by determining the processor type of the compiling machine. Using -march=native enables all instruction subsets supported by the local machine and will produce code optimized for the local -machine under the constraints of the selected instruction set."[2] +machine under the constraints of the selected instruction set."[3] -Do NOT try using the 'native' option on AMD Piledriver, Steamroller, or -Excavator CPUs (-march=bdver{2,3,4} flag). The build will error out due the -kernel's objtool issue with these.[3a,b] +Users of Intel CPUs should select the 'Intel-Native' option and users of AMD +CPUs should select the 'AMD-Native' option. -MINOR NOTES -This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9 -changes. Note that upstream is using the deprecated 'match=atom' flags when I -believe it should use the newer 'march=bonnell' flag for atom processors.[4] +MINOR NOTES RELATING TO INTEL ATOM PROCESSORS +This patch also changes -march=atom to -march=bonnell in accordance with the +gcc v4.9 changes. Upstream is using the deprecated -match=atom flags when I +believe it should use the newer -march=bonnell flag for atom processors.[4] It is not recommended to compile on Atom-CPUs with the 'native' option.[5] The recommendation is to use the 'atom' option instead. @@ -72,28 +90,26 @@ https://github.com/graysky2/kernel_gcc_patch REQUIREMENTS linux version >=5.8 -gcc version >=10.1 +gcc version >=9.0 ACKNOWLEDGMENTS This patch builds on the seminal work by Jeroen.[6] REFERENCES 1. https://gcc.gnu.org/gcc-4.9/changes.html -2. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html -3a. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95671#c11 -3b. https://github.com/graysky2/kernel_gcc_patch/issues/55 +2. https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/77566eb03bc6a326811cb7e9 +3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html#index-x86-Options 4. https://bugzilla.kernel.org/show_bug.cgi?id=77461 5. https://github.com/graysky2/kernel_gcc_patch/issues/15 6. http://www.linuxforge.net/docs/linux/linux-gcc.php - --- - arch/x86/Kconfig.cpu | 258 ++++++++++++++++++++++++++++++-- - arch/x86/Makefile | 39 ++++- - arch/x86/include/asm/vermagic.h | 56 +++++++ - 3 files changed, 336 insertions(+), 17 deletions(-) + arch/x86/Kconfig.cpu | 332 ++++++++++++++++++++++++++++++-- + arch/x86/Makefile | 47 ++++- + arch/x86/include/asm/vermagic.h | 66 +++++++ + 3 files changed, 428 insertions(+), 17 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu -index 814fe0d349b0..134390e619bb 100644 +index 814fe0d349b0..872b9cf598e3 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -157,7 +157,7 @@ config MPENTIUM4 @@ -114,7 +130,7 @@ index 814fe0d349b0..134390e619bb 100644 depends on X86_32 help Select this for an AMD Athlon K7-family processor. Enables use of -@@ -173,12 +173,90 @@ config MK7 +@@ -173,12 +173,98 @@ config MK7 flags to GCC. config MK8 @@ -202,11 +218,19 @@ index 814fe0d349b0..134390e619bb 100644 + Select this for AMD Family 17h Zen 2 processors. + + Enables -march=znver2 ++ ++config MZEN3 ++ bool "AMD Zen 3" ++ depends on GCC_VERSION > 100300 ++ help ++ Select this for AMD Family 19h Zen 3 processors. ++ ++ Enables -march=znver3 + config MCRUSOE bool "Crusoe" depends on X86_32 -@@ -270,7 +348,7 @@ config MPSC +@@ -270,7 +356,7 @@ config MPSC in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. config MCORE2 @@ -215,7 +239,7 @@ index 814fe0d349b0..134390e619bb 100644 help Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and -@@ -278,6 +356,8 @@ config MCORE2 +@@ -278,6 +364,8 @@ config MCORE2 family in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo) @@ -224,7 +248,7 @@ index 814fe0d349b0..134390e619bb 100644 config MATOM bool "Intel Atom" help -@@ -287,6 +367,150 @@ config MATOM +@@ -287,6 +375,182 @@ config MATOM accordingly optimized code. Use a recent GCC with specific Atom support in order to fully benefit from selecting this option. @@ -356,6 +380,7 @@ index 814fe0d349b0..134390e619bb 100644 + +config MCOOPERLAKE + bool "Intel Cooper Lake" ++ depends on GCC_VERSION > 100100 + select X86_P6_NOP + help + @@ -365,22 +390,77 @@ index 814fe0d349b0..134390e619bb 100644 + +config MTIGERLAKE + bool "Intel Tiger Lake" ++ depends on GCC_VERSION > 100100 + select X86_P6_NOP + help + + Select this for third-generation 10 nm process processors in the Tiger Lake family. + + Enables -march=tigerlake ++ ++config MSAPPHIRERAPIDS ++ bool "Intel Sapphire Rapids" ++ depends on GCC_VERSION > 110000 ++ select X86_P6_NOP ++ help ++ ++ Select this for third-generation 10 nm process processors in the Sapphire Rapids family. ++ ++ Enables -march=sapphirerapids ++ ++config MROCKETLAKE ++ bool "Intel Rocket Lake" ++ depends on GCC_VERSION > 110000 ++ select X86_P6_NOP ++ help ++ ++ Select this for eleventh-generation processors in the Rocket Lake family. ++ ++ Enables -march=rocketlake ++ ++config MALDERLAKE ++ bool "Intel Alder Lake" ++ depends on GCC_VERSION > 110000 ++ select X86_P6_NOP ++ help ++ ++ Select this for twelfth-generation processors in the Alder Lake family. ++ ++ Enables -march=alderlake + config GENERIC_CPU bool "Generic-x86-64" depends on X86_64 -@@ -294,6 +518,16 @@ config GENERIC_CPU +@@ -294,6 +558,50 @@ config GENERIC_CPU Generic x86-64 CPU. Run equally well on all x86-64 CPUs. -+config MNATIVE -+ bool "Native optimizations autodetected by GCC" ++config GENERIC_CPU2 ++ bool "Generic-x86-64-v2" ++ depends on GCC_VERSION > 110000 ++ depends on X86_64 ++ help ++ Generic x86-64 CPU. ++ Run equally well on all x86-64 CPUs with min support of x86-64-v2. ++ ++config GENERIC_CPU3 ++ bool "Generic-x86-64-v3" ++ depends on GCC_VERSION > 110000 ++ depends on X86_64 ++ help ++ Generic x86-64-v3 CPU with v3 instructions. ++ Run equally well on all x86-64 CPUs with min support of x86-64-v3. ++ ++config GENERIC_CPU4 ++ bool "Generic-x86-64-v4" ++ depends on GCC_VERSION > 110000 ++ depends on X86_64 ++ help ++ Generic x86-64 CPU with v4 instructions. ++ Run equally well on all x86-64 CPUs with min support of x86-64-v4. ++ ++config MNATIVE_INTEL ++ bool "Intel-Native optimizations autodetected by GCC" + help + + GCC 4.2 and above support -march=native, which automatically detects @@ -388,70 +468,80 @@ index 814fe0d349b0..134390e619bb 100644 + for AMD CPUs. Intel Only! + + Enables -march=native ++ ++config MNATIVE_AMD ++ bool "AMD-Native optimizations autodetected by GCC" ++ help ++ ++ GCC 4.2 and above support -march=native, which automatically detects ++ the optimum settings to use based on your processor. Do NOT use this ++ for Intel CPUs. AMD Only! ++ ++ Enables -march=native + endchoice config X86_GENERIC -@@ -318,7 +552,7 @@ config X86_INTERNODE_CACHE_SHIFT +@@ -318,7 +626,7 @@ config X86_INTERNODE_CACHE_SHIFT config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 || MPSC - default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU -+ default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE || X86_GENERIC || GENERIC_CPU ++ default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD || X86_GENERIC || GENERIC_CPU || GENERIC_CPU2 || GENERIC_CPU3 || GENERIC_CPU4 default "4" if MELAN || M486SX || M486 || MGEODEGX1 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX -@@ -336,11 +570,11 @@ config X86_ALIGNMENT_16 +@@ -336,11 +644,11 @@ config X86_ALIGNMENT_16 config X86_INTEL_USERCOPY def_bool y - depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 -+ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE ++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL config X86_USE_PPRO_CHECKSUM def_bool y - depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM -+ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE ++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD config X86_USE_3DNOW def_bool y -@@ -360,26 +594,26 @@ config X86_USE_3DNOW +@@ -360,26 +668,26 @@ config X86_USE_3DNOW config X86_P6_NOP def_bool y depends on X86_64 - depends on (MCORE2 || MPENTIUM4 || MPSC) -+ depends on (MCORE2 || MPENTIUM4 || MPSC || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE) ++ depends on (MCORE2 || MPENTIUM4 || MPSC || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL) config X86_TSC def_bool y - depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 -+ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE) || X86_64 ++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD) || X86_64 config X86_CMPXCHG64 def_bool y - depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 -+ depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE ++ depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD # this should be set for all -march=.. options where the compiler # generates cmov. config X86_CMOV def_bool y - depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) -+ depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE) ++ depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD) config X86_MINIMUM_CPU_FAMILY int default "64" if X86_64 - default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8) -+ default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MNATIVE) ++ default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD) default "5" if X86_32 && X86_CMPXCHG64 default "4" diff --git a/arch/x86/Makefile b/arch/x86/Makefile -index 7116da3980be..50c8af35092b 100644 +index 9a85eae37b17..facf9a278fe3 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile -@@ -110,11 +110,40 @@ else +@@ -113,11 +113,48 @@ else # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) @@ -473,9 +563,11 @@ index 7116da3980be..50c8af35092b 100644 + cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4) + cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-mno-tbm) + cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1) -+ cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2) ++ cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2) ++ cflags-$(CONFIG_MZEN3) += $(call cc-option,-march=znver3) + -+ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) ++ cflags-$(CONFIG_MNATIVE_INTEL) += $(call cc-option,-march=native) ++ cflags-$(CONFIG_MNATIVE_AMD) += $(call cc-option,-march=native) + cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) + cflags-$(CONFIG_MCORE2) += $(call cc-option,-march=core2) + cflags-$(CONFIG_MNEHALEM) += $(call cc-option,-march=nehalem) @@ -494,19 +586,27 @@ index 7116da3980be..50c8af35092b 100644 + cflags-$(CONFIG_MCASCADELAKE) += $(call cc-option,-march=cascadelake) + cflags-$(CONFIG_MCOOPERLAKE) += $(call cc-option,-march=cooperlake) + cflags-$(CONFIG_MTIGERLAKE) += $(call cc-option,-march=tigerlake) ++ cflags-$(CONFIG_MSAPPHIRERAPIDS) += $(call cc-option,-march=sapphirerapids) ++ cflags-$(CONFIG_MROCKETLAKE) += $(call cc-option,-march=rocketlake) ++ cflags-$(CONFIG_MALDERLAKE) += $(call cc-option,-march=alderlake) ++ cflags-$(CONFIG_GENERIC_CPU2) += $(call cc-option,-march=x86-64-v2) ++ cflags-$(CONFIG_GENERIC_CPU3) += $(call cc-option,-march=x86-64-v3) ++ cflags-$(CONFIG_GENERIC_CPU4) += $(call cc-option,-march=x86-64-v4) cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic) KBUILD_CFLAGS += $(cflags-y) diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagic.h -index 75884d2cdec3..14c222e78213 100644 +index 75884d2cdec3..4e6a08d4c7e5 100644 --- a/arch/x86/include/asm/vermagic.h +++ b/arch/x86/include/asm/vermagic.h -@@ -17,6 +17,40 @@ +@@ -17,6 +17,48 @@ #define MODULE_PROC_FAMILY "586MMX " #elif defined CONFIG_MCORE2 #define MODULE_PROC_FAMILY "CORE2 " -+#elif defined CONFIG_MNATIVE -+#define MODULE_PROC_FAMILY "NATIVE " ++#elif defined CONFIG_MNATIVE_INTEL ++#define MODULE_PROC_FAMILY "NATIVE_INTEL " ++#elif defined CONFIG_MNATIVE_AMD ++#define MODULE_PROC_FAMILY "NATIVE_AMD " +#elif defined CONFIG_MNEHALEM +#define MODULE_PROC_FAMILY "NEHALEM " +#elif defined CONFIG_MWESTMERE @@ -539,10 +639,16 @@ index 75884d2cdec3..14c222e78213 100644 +#define MODULE_PROC_FAMILY "COOPERLAKE " +#elif defined CONFIG_MTIGERLAKE +#define MODULE_PROC_FAMILY "TIGERLAKE " ++#elif defined CONFIG_MSAPPHIRERAPIDS ++#define MODULE_PROC_FAMILY "SAPPHIRERAPIDS " ++#elif defined CONFIG_ROCKETLAKE ++#define MODULE_PROC_FAMILY "ROCKETLAKE " ++#elif defined CONFIG_MALDERLAKE ++#define MODULE_PROC_FAMILY "ALDERLAKE " #elif defined CONFIG_MATOM #define MODULE_PROC_FAMILY "ATOM " #elif defined CONFIG_M686 -@@ -35,6 +69,28 @@ +@@ -35,6 +77,30 @@ #define MODULE_PROC_FAMILY "K7 " #elif defined CONFIG_MK8 #define MODULE_PROC_FAMILY "K8 " @@ -568,10 +674,11 @@ index 75884d2cdec3..14c222e78213 100644 +#define MODULE_PROC_FAMILY "ZEN " +#elif defined CONFIG_MZEN2 +#define MODULE_PROC_FAMILY "ZEN2 " ++#elif defined CONFIG_MZEN3 ++#define MODULE_PROC_FAMILY "ZEN3 " #elif defined CONFIG_MELAN #define MODULE_PROC_FAMILY "ELAN " #elif defined CONFIG_MCRUSOE -- -2.30.1 - +2.31.1 diff --git a/5020_BMQ-and-PDS-io-scheduler-v5.11-r2.patch b/5020_BMQ-and-PDS-io-scheduler-v5.11-r3.patch similarity index 99% rename from 5020_BMQ-and-PDS-io-scheduler-v5.11-r2.patch rename to 5020_BMQ-and-PDS-io-scheduler-v5.11-r3.patch index f5d03d9..78af67f 100644 --- a/5020_BMQ-and-PDS-io-scheduler-v5.11-r2.patch +++ b/5020_BMQ-and-PDS-io-scheduler-v5.11-r3.patch @@ -837,10 +837,10 @@ index 5fc9c9b70862..eb6d7d87779f 100644 obj-$(CONFIG_CPU_FREQ_GOV_SCHEDUTIL) += cpufreq_schedutil.o diff --git a/kernel/sched/alt_core.c b/kernel/sched/alt_core.c new file mode 100644 -index 000000000000..7b99fdbb48df +index 000000000000..0066b97100bb --- /dev/null +++ b/kernel/sched/alt_core.c -@@ -0,0 +1,6910 @@ +@@ -0,0 +1,6914 @@ +/* + * kernel/sched/alt_core.c + * @@ -895,7 +895,7 @@ index 000000000000..7b99fdbb48df + */ +EXPORT_TRACEPOINT_SYMBOL_GPL(pelt_irq_tp); + -+#define ALT_SCHED_VERSION "v5.11-r2" ++#define ALT_SCHED_VERSION "v5.11-r3" + +/* rt_prio(prio) defined in include/linux/sched/rt.h */ +#define rt_task(p) rt_prio((p)->prio) @@ -2026,6 +2026,9 @@ index 000000000000..7b99fdbb48df +{ + struct task_struct *p = current; + ++ if (0 == p->migration_disabled) ++ return; ++ + if (p->migration_disabled > 1) { + p->migration_disabled--; + return; @@ -4232,7 +4235,8 @@ index 000000000000..7b99fdbb48df + rq->active_balance = 0; + /* _something_ may have changed the task, double check again */ + if (task_on_rq_queued(p) && task_rq(p) == rq && -+ cpumask_and(&tmp, p->cpus_ptr, &sched_sg_idle_mask)) { ++ cpumask_and(&tmp, p->cpus_ptr, &sched_sg_idle_mask) && ++ !is_migration_disabled(p)) { + int cpu = cpu_of(rq); + int dcpu = __best_mask_cpu(cpu, &tmp, + per_cpu(sched_cpu_llc_mask, cpu)); @@ -4260,7 +4264,7 @@ index 000000000000..7b99fdbb48df + curr = rq->curr; + res = (!is_idle_task(curr)) && (1 == rq->nr_running) &&\ + cpumask_intersects(curr->cpus_ptr, &sched_sg_idle_mask) &&\ -+ (!rq->active_balance); ++ !is_migration_disabled(curr) && (!rq->active_balance); + + if (res) + rq->active_balance = 1; @@ -7790,10 +7794,10 @@ index 000000000000..1212a031700e +{} diff --git a/kernel/sched/alt_sched.h b/kernel/sched/alt_sched.h new file mode 100644 -index 000000000000..51f11bf416f4 +index 000000000000..7bcd96cc6bed --- /dev/null +++ b/kernel/sched/alt_sched.h -@@ -0,0 +1,683 @@ +@@ -0,0 +1,684 @@ +#ifndef ALT_SCHED_H +#define ALT_SCHED_H + @@ -8394,7 +8398,8 @@ index 000000000000..51f11bf416f4 +{ + struct update_util_data *data; + -+ data = rcu_dereference_sched(*this_cpu_ptr(&cpufreq_update_util_data)); ++ data = rcu_dereference_sched(*per_cpu_ptr(&cpufreq_update_util_data, ++ cpu_of(rq))); + if (data) + data->func(data, rq_clock(rq), flags); +} @@ -8704,7 +8709,7 @@ index 000000000000..13eda4b26b6a + boost_task(p); +} diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c -index 6931f0cdeb80..0c074c53c60a 100644 +index 6931f0cdeb80..c5e3d3839650 100644 --- a/kernel/sched/cpufreq_schedutil.c +++ b/kernel/sched/cpufreq_schedutil.c @@ -171,6 +171,7 @@ static unsigned int get_next_freq(struct sugov_policy *sg_policy, @@ -8715,31 +8720,37 @@ index 6931f0cdeb80..0c074c53c60a 100644 /* * This function computes an effective utilization for the given CPU, to be * used for frequency selection given the linear relation: f = u * f_max. -@@ -287,6 +288,13 @@ static void sugov_get_util(struct sugov_cpu *sg_cpu) - sg_cpu->util = schedutil_cpu_util(sg_cpu->cpu, cpu_util_cfs(rq), max, +@@ -288,6 +289,18 @@ static void sugov_get_util(struct sugov_cpu *sg_cpu) FREQUENCY_UTIL, NULL); } + +#else /* CONFIG_SCHED_ALT */ -+static unsigned long sugov_get_util(struct sugov_cpu *sg_cpu) ++ ++static void sugov_get_util(struct sugov_cpu *sg_cpu) +{ -+ sg_cpu->max = arch_scale_cpu_capacity(sg_cpu->cpu); -+ return sg_cpu->max; ++ unsigned long max = arch_scale_cpu_capacity(sg_cpu->cpu); ++ ++ sg_cpu->max = max; ++ sg_cpu->bw_dl = 0; ++ sg_cpu->util = cpu_rq(sg_cpu->cpu)->nr_running ? max:0UL; +} +#endif - ++ /** * sugov_iowait_reset() - Reset the IO boost status of a CPU. -@@ -428,7 +436,9 @@ static inline bool sugov_cpu_is_busy(struct sugov_cpu *sg_cpu) { return false; } + * @sg_cpu: the sugov data for the CPU to boost +@@ -428,8 +441,10 @@ static inline bool sugov_cpu_is_busy(struct sugov_cpu *sg_cpu) { return false; } */ static inline void ignore_dl_rate_limit(struct sugov_cpu *sg_cpu, struct sugov_policy *sg_policy) { +#ifndef CONFIG_SCHED_ALT if (cpu_bw_dl(cpu_rq(sg_cpu->cpu)) > sg_cpu->bw_dl) -+#endif sg_policy->limits_changed = true; ++#endif } -@@ -711,6 +721,7 @@ static int sugov_kthread_create(struct sugov_policy *sg_policy) + static inline bool sugov_update_single_common(struct sugov_cpu *sg_cpu, +@@ -711,6 +726,7 @@ static int sugov_kthread_create(struct sugov_policy *sg_policy) } ret = sched_setattr_nocheck(thread, &attr); @@ -8747,7 +8758,7 @@ index 6931f0cdeb80..0c074c53c60a 100644 if (ret) { kthread_stop(thread); pr_warn("%s: failed to set SCHED_DEADLINE\n", __func__); -@@ -943,6 +954,7 @@ struct cpufreq_governor *cpufreq_default_governor(void) +@@ -943,6 +959,7 @@ struct cpufreq_governor *cpufreq_default_governor(void) cpufreq_governor_init(schedutil_gov); #ifdef CONFIG_ENERGY_MODEL @@ -8755,7 +8766,7 @@ index 6931f0cdeb80..0c074c53c60a 100644 static void rebuild_sd_workfn(struct work_struct *work) { rebuild_sched_domains_energy(); -@@ -966,4 +978,10 @@ void sched_cpufreq_governor_change(struct cpufreq_policy *policy, +@@ -966,4 +983,10 @@ void sched_cpufreq_governor_change(struct cpufreq_policy *policy, } }
