commit:     5413402d5ae386897d24ac39a7755de77ef3d9c5
Author:     Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org>
AuthorDate: Tue Jun 15 14:18:23 2021 +0000
Commit:     Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org>
CommitDate: Tue Jun 15 14:18:37 2021 +0000
URL:        https://gitweb.gentoo.org/proj/releng.git/commit/?id=5413402d

Fix riscv upload instructions

Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org>

 tools/catalyst-auto-qemu-riscv.conf | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/tools/catalyst-auto-qemu-riscv.conf 
b/tools/catalyst-auto-qemu-riscv.conf
index d6fed219..a1ebcf8e 100644
--- a/tools/catalyst-auto-qemu-riscv.conf
+++ b/tools/catalyst-auto-qemu-riscv.conf
@@ -51,16 +51,19 @@ update_symlinks() {
 post_build() {
        local set=$1 spec=$2
 
-       pushd "${BUILD_SRCDIR_BASE}/builds/default" >/dev/null
-
        case ${spec} in
+               stage3*lp64*20.0*.spec)
+                       pushd "${BUILD_SRCDIR_BASE}/builds/20.0" >/dev/null
+                       upload stage3-rv64_$(echo ${spec}|sed -e 
's:^stage3-::g' -e 's:\.spec$::g')-${TIMESTAMP}*.xz*
+                       popd >/dev/null
+                       ;;
                stage3*lp64*.spec)
+                       pushd "${BUILD_SRCDIR_BASE}/builds/default" >/dev/null
                        upload stage3-rv64_$(echo ${spec}|sed -e 
's:^stage3-::g' -e 's:\.spec$::g')-${TIMESTAMP}*.xz*
+                       popd >/dev/null
+                       ;;
+               *)
+                       echo "Finished ${spec}"
                        ;;
-       *)
-               echo "Finished ${spec}"
-               ;;
        esac
-
-       popd >/dev/null
 }

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