commit: 4f2fd56455090dfa618857616f3ca1afc10663e3
Author: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org>
AuthorDate: Sat Jul 30 18:41:18 2022 +0000
Commit: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org>
CommitDate: Sat Jul 30 18:41:18 2022 +0000
URL: https://gitweb.gentoo.org/proj/catalyst.git/commit/?id=4f2fd564
arch: Add subarch definition for riscv64 softfloat musl
Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org>
catalyst/arch/riscv.py | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/catalyst/arch/riscv.py b/catalyst/arch/riscv.py
index d7b76c37..975bce99 100644
--- a/catalyst/arch/riscv.py
+++ b/catalyst/arch/riscv.py
@@ -34,6 +34,12 @@ class arch_rv64_lp64(generic_riscv):
def __init__(self,myspec):
generic_riscv.__init__(self,myspec)
+class arch_rv64_lp64_musl(generic_riscv):
+ "builder class for rv64_lp64_musl"
+ def __init__(self,myspec):
+ generic_riscv.__init__(self,myspec)
+ self.settings["CHOST"]="riscv64-gentoo-linux-musl"
+
class arch_rv32_ilp32d(generic_riscv):
"builder class for rv32_ilp32d"
def __init__(self,myspec):
