commit: b3e6664fbe92c3787a56b3f0f64a08c2ff24f6ee Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Fri Sep 23 12:38:23 2022 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Fri Sep 23 12:38:23 2022 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=b3e6664f
Linux patch 5.19.11 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> 0000_README | 4 + 1010_linux-5.19.11.patch | 1231 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 1235 insertions(+) diff --git a/0000_README b/0000_README index e710df97..d3eec191 100644 --- a/0000_README +++ b/0000_README @@ -83,6 +83,10 @@ Patch: 1009_linux-5.19.10.patch From: http://www.kernel.org Desc: Linux 5.19.10 +Patch: 1010_linux-5.19.11.patch +From: http://www.kernel.org +Desc: Linux 5.19.11 + Patch: 1500_XATTR_USER_PREFIX.patch From: https://bugs.gentoo.org/show_bug.cgi?id=470644 Desc: Support for namespace user.pax.* on tmpfs. diff --git a/1010_linux-5.19.11.patch b/1010_linux-5.19.11.patch new file mode 100644 index 00000000..a5ff5cbf --- /dev/null +++ b/1010_linux-5.19.11.patch @@ -0,0 +1,1231 @@ +diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +index 85c85b694217c..e18107eafe7cc 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +@@ -96,7 +96,7 @@ properties: + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: +- - fiq-index ++ - apple,fiq-index + - cpus + + required: +diff --git a/Makefile b/Makefile +index 33a9b6b547c47..01463a22926d5 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + VERSION = 5 + PATCHLEVEL = 19 +-SUBLEVEL = 10 ++SUBLEVEL = 11 + EXTRAVERSION = + NAME = Superb Owl + +diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig +index cd2b3fe156724..c68c3581483ac 100644 +--- a/arch/parisc/Kconfig ++++ b/arch/parisc/Kconfig +@@ -225,8 +225,18 @@ config MLONGCALLS + Enabling this option will probably slow down your kernel. + + config 64BIT +- def_bool "$(ARCH)" = "parisc64" ++ def_bool y if "$(ARCH)" = "parisc64" ++ bool "64-bit kernel" if "$(ARCH)" = "parisc" + depends on PA8X00 ++ help ++ Enable this if you want to support 64bit kernel on PA-RISC platform. ++ ++ At the moment, only people willing to use more than 2GB of RAM, ++ or having a 64bit-only capable PA-RISC machine should say Y here. ++ ++ Since there is no 64bit userland on PA-RISC, there is no point to ++ enable this option otherwise. The 64bit kernel is significantly bigger ++ and slower than the 32bit one. + + choice + prompt "Kernel page size" +diff --git a/block/blk-core.c b/block/blk-core.c +index 27fb1357ad4b8..cc6fbcb6d2521 100644 +--- a/block/blk-core.c ++++ b/block/blk-core.c +@@ -338,7 +338,7 @@ int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags) + + while (!blk_try_enter_queue(q, pm)) { + if (flags & BLK_MQ_REQ_NOWAIT) +- return -EBUSY; ++ return -EAGAIN; + + /* + * read pair of barrier in blk_freeze_queue_start(), we need to +@@ -368,7 +368,7 @@ int __bio_queue_enter(struct request_queue *q, struct bio *bio) + if (test_bit(GD_DEAD, &disk->state)) + goto dead; + bio_wouldblock_error(bio); +- return -EBUSY; ++ return -EAGAIN; + } + + /* +diff --git a/block/blk-lib.c b/block/blk-lib.c +index 09b7e1200c0f4..20e42144065b8 100644 +--- a/block/blk-lib.c ++++ b/block/blk-lib.c +@@ -311,6 +311,11 @@ int blkdev_issue_secure_erase(struct block_device *bdev, sector_t sector, + struct blk_plug plug; + int ret = 0; + ++ /* make sure that "len << SECTOR_SHIFT" doesn't overflow */ ++ if (max_sectors > UINT_MAX >> SECTOR_SHIFT) ++ max_sectors = UINT_MAX >> SECTOR_SHIFT; ++ max_sectors &= ~bs_mask; ++ + if (max_sectors == 0) + return -EOPNOTSUPP; + if ((sector | nr_sects) & bs_mask) +@@ -324,10 +329,10 @@ int blkdev_issue_secure_erase(struct block_device *bdev, sector_t sector, + + bio = blk_next_bio(bio, bdev, 0, REQ_OP_SECURE_ERASE, gfp); + bio->bi_iter.bi_sector = sector; +- bio->bi_iter.bi_size = len; ++ bio->bi_iter.bi_size = len << SECTOR_SHIFT; + +- sector += len << SECTOR_SHIFT; +- nr_sects -= len << SECTOR_SHIFT; ++ sector += len; ++ nr_sects -= len; + if (!nr_sects) { + ret = submit_bio_wait(bio); + bio_put(bio); +diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c +index a964e25ea6206..763256efddc2b 100644 +--- a/drivers/gpio/gpio-mpc8xxx.c ++++ b/drivers/gpio/gpio-mpc8xxx.c +@@ -172,6 +172,7 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) + + switch (flow_type) { + case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: + raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); + gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, + gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index e342a6dc4c6c1..bb953f6478647 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -418,11 +418,11 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + goto out; + } else { + bank->toggle_edge_mode |= mask; +- level |= mask; ++ level &= ~mask; + + /* + * Determine gpio state. If 1 next interrupt should be +- * falling otherwise rising. ++ * low otherwise high. + */ + data = readl(bank->reg_base + bank->gpio_regs->ext_port); + if (data & mask) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 67d4a3c13ed19..929f8b75bfaee 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2391,8 +2391,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) + } + adev->ip_blocks[i].status.sw = true; + +- /* need to do gmc hw init early so we can allocate gpu mem */ +- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { ++ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { ++ /* need to do common hw init early so everything is set up for gmc */ ++ r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); ++ if (r) { ++ DRM_ERROR("hw_init %d failed %d\n", i, r); ++ goto init_failed; ++ } ++ adev->ip_blocks[i].status.hw = true; ++ } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { ++ /* need to do gmc hw init early so we can allocate gpu mem */ + /* Try to reserve bad pages early */ + if (amdgpu_sriov_vf(adev)) + amdgpu_virt_exchange_data(adev); +@@ -3078,8 +3086,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) + int i, r; + + static enum amd_ip_block_type ip_order[] = { +- AMD_IP_BLOCK_TYPE_GMC, + AMD_IP_BLOCK_TYPE_COMMON, ++ AMD_IP_BLOCK_TYPE_GMC, + AMD_IP_BLOCK_TYPE_PSP, + AMD_IP_BLOCK_TYPE_IH, + }; +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +index f49db13b3fbee..0debdbcf46310 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +@@ -380,6 +380,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, + WREG32_PCIE(smnPCIE_LC_CNTL, data); + } + ++#ifdef CONFIG_PCIEASPM + static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) + { + uint32_t def, data; +@@ -401,9 +402,11 @@ static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) + if (def != data) + WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); + } ++#endif + + static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) + { ++#ifdef CONFIG_PCIEASPM + uint32_t def, data; + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); +@@ -459,7 +462,10 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL6, data); + +- nbio_v2_3_program_ltr(adev); ++ /* Don't bother about LTR if LTR is not enabled ++ * in the path */ ++ if (adev->pdev->ltr_path) ++ nbio_v2_3_program_ltr(adev); + + def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); + data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; +@@ -483,6 +489,7 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) + data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL3, data); ++#endif + } + + static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev) +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +index f7f6ddebd3e49..37615a77287bc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +@@ -282,6 +282,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev) + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; + } + ++#ifdef CONFIG_PCIEASPM + static void nbio_v6_1_program_ltr(struct amdgpu_device *adev) + { + uint32_t def, data; +@@ -303,9 +304,11 @@ static void nbio_v6_1_program_ltr(struct amdgpu_device *adev) + if (def != data) + WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); + } ++#endif + + static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) + { ++#ifdef CONFIG_PCIEASPM + uint32_t def, data; + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); +@@ -361,7 +364,10 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL6, data); + +- nbio_v6_1_program_ltr(adev); ++ /* Don't bother about LTR if LTR is not enabled ++ * in the path */ ++ if (adev->pdev->ltr_path) ++ nbio_v6_1_program_ltr(adev); + + def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); + data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; +@@ -385,6 +391,7 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) + data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL3, data); ++#endif + } + + const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +index 11848d1e238b6..19455a7259391 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +@@ -673,6 +673,7 @@ struct amdgpu_nbio_ras nbio_v7_4_ras = { + }; + + ++#ifdef CONFIG_PCIEASPM + static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) + { + uint32_t def, data; +@@ -694,9 +695,11 @@ static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) + if (def != data) + WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); + } ++#endif + + static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) + { ++#ifdef CONFIG_PCIEASPM + uint32_t def, data; + + if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4)) +@@ -755,7 +758,10 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL6, data); + +- nbio_v7_4_program_ltr(adev); ++ /* Don't bother about LTR if LTR is not enabled ++ * in the path */ ++ if (adev->pdev->ltr_path) ++ nbio_v7_4_program_ltr(adev); + + def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); + data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; +@@ -779,6 +785,7 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) + data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL3, data); ++#endif + } + + const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 65181efba50ec..56424f75dd2cc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -1504,6 +1504,11 @@ static int sdma_v4_0_start(struct amdgpu_device *adev) + WREG32_SDMA(i, mmSDMA0_CNTL, temp); + + if (!amdgpu_sriov_vf(adev)) { ++ ring = &adev->sdma.instance[i].ring; ++ adev->nbio.funcs->sdma_doorbell_range(adev, i, ++ ring->use_doorbell, ring->doorbell_index, ++ adev->doorbell_index.sdma_doorbell_range); ++ + /* unhalt engine */ + temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index fde6154f20096..183024d7c184e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -1211,25 +1211,6 @@ static int soc15_common_sw_fini(void *handle) + return 0; + } + +-static void soc15_doorbell_range_init(struct amdgpu_device *adev) +-{ +- int i; +- struct amdgpu_ring *ring; +- +- /* sdma/ih doorbell range are programed by hypervisor */ +- if (!amdgpu_sriov_vf(adev)) { +- for (i = 0; i < adev->sdma.num_instances; i++) { +- ring = &adev->sdma.instance[i].ring; +- adev->nbio.funcs->sdma_doorbell_range(adev, i, +- ring->use_doorbell, ring->doorbell_index, +- adev->doorbell_index.sdma_doorbell_range); +- } +- +- adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, +- adev->irq.ih.doorbell_index); +- } +-} +- + static int soc15_common_hw_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +@@ -1249,12 +1230,6 @@ static int soc15_common_hw_init(void *handle) + + /* enable the doorbell aperture */ + soc15_enable_doorbell_aperture(adev, true); +- /* HW doorbell routing policy: doorbell writing not +- * in SDMA/IH/MM/ACV range will be routed to CP. So +- * we need to init SDMA/IH/MM/ACV doorbell range prior +- * to CP ip block init and ring test. +- */ +- soc15_doorbell_range_init(adev); + + return 0; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +index 03b7066471f9a..1e83db0c5438d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +@@ -289,6 +289,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) + } + } + ++ if (!amdgpu_sriov_vf(adev)) ++ adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, ++ adev->irq.ih.doorbell_index); ++ + pci_set_master(adev->pdev); + + /* enable interrupts */ +diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +index 2022ffbb8dba5..59dfca093155c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +@@ -340,6 +340,10 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev) + } + } + ++ if (!amdgpu_sriov_vf(adev)) ++ adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, ++ adev->irq.ih.doorbell_index); ++ + pci_set_master(adev->pdev); + + /* enable interrupts */ +diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c +index 19bf717fd4cb6..5508ebb9eb434 100644 +--- a/drivers/gpu/drm/i915/display/icl_dsi.c ++++ b/drivers/gpu/drm/i915/display/icl_dsi.c +@@ -1629,6 +1629,8 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, + /* FIXME: initialize from VBT */ + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; + ++ vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; ++ + ret = intel_dsc_compute_params(crtc_state); + if (ret) + return ret; +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 41aaa6c98114f..fe8b6b72970a2 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -1379,6 +1379,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, + * DP_DSC_RC_BUF_SIZE for this. + */ + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; ++ vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; + + /* + * Slice Height of 8 works for all currently available panels. So start +diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c +index 43e1bbc1e3035..ca530f0733e0e 100644 +--- a/drivers/gpu/drm/i915/display/intel_vdsc.c ++++ b/drivers/gpu/drm/i915/display/intel_vdsc.c +@@ -460,7 +460,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) + u8 i = 0; + + vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; +- vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; + vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, + pipe_config->dsc.slice_count); + +diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h +index 9feda105f9131..a7acffbf15d1f 100644 +--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h ++++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h +@@ -235,6 +235,14 @@ struct intel_guc { + * @shift: Right shift value for the gpm timestamp + */ + u32 shift; ++ ++ /** ++ * @last_stat_jiffies: jiffies at last actual stats collection time ++ * We use this timestamp to ensure we don't oversample the ++ * stats because runtime power management events can trigger ++ * stats collection at much higher rates than required. ++ */ ++ unsigned long last_stat_jiffies; + } timestamp; + + #ifdef CONFIG_DRM_I915_SELFTEST +diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +index 26a051ef119df..d7e4681d7297c 100644 +--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ++++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +@@ -1365,6 +1365,8 @@ static void __update_guc_busyness_stats(struct intel_guc *guc) + unsigned long flags; + ktime_t unused; + ++ guc->timestamp.last_stat_jiffies = jiffies; ++ + spin_lock_irqsave(&guc->timestamp.lock, flags); + + guc_update_pm_timestamp(guc, &unused); +@@ -1436,7 +1438,23 @@ void intel_guc_busyness_park(struct intel_gt *gt) + if (!guc_submission_initialized(guc)) + return; + +- cancel_delayed_work(&guc->timestamp.work); ++ /* ++ * There is a race with suspend flow where the worker runs after suspend ++ * and causes an unclaimed register access warning. Cancel the worker ++ * synchronously here. ++ */ ++ cancel_delayed_work_sync(&guc->timestamp.work); ++ ++ /* ++ * Before parking, we should sample engine busyness stats if we need to. ++ * We can skip it if we are less than half a ping from the last time we ++ * sampled the busyness stats. ++ */ ++ if (guc->timestamp.last_stat_jiffies && ++ !time_after(jiffies, guc->timestamp.last_stat_jiffies + ++ (guc->timestamp.ping_delay / 2))) ++ return; ++ + __update_guc_busyness_stats(guc); + } + +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index 4f5a51bb9e1e4..e77956ae88a4b 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -1849,14 +1849,14 @@ + + #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) + #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 +-#define PROCHOT_MASK REG_BIT(1) +-#define THERMAL_LIMIT_MASK REG_BIT(2) +-#define RATL_MASK REG_BIT(6) +-#define VR_THERMALERT_MASK REG_BIT(7) +-#define VR_TDC_MASK REG_BIT(8) +-#define POWER_LIMIT_4_MASK REG_BIT(9) +-#define POWER_LIMIT_1_MASK REG_BIT(11) +-#define POWER_LIMIT_2_MASK REG_BIT(12) ++#define PROCHOT_MASK REG_BIT(0) ++#define THERMAL_LIMIT_MASK REG_BIT(1) ++#define RATL_MASK REG_BIT(5) ++#define VR_THERMALERT_MASK REG_BIT(6) ++#define VR_TDC_MASK REG_BIT(7) ++#define POWER_LIMIT_4_MASK REG_BIT(8) ++#define POWER_LIMIT_1_MASK REG_BIT(10) ++#define POWER_LIMIT_2_MASK REG_BIT(11) + + #define CHV_CLK_CTL1 _MMIO(0x101100) + #define VLV_CLK_CTL2 _MMIO(0x101104) +diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c +index 16460b169ed21..2a32729a74b51 100644 +--- a/drivers/gpu/drm/i915/i915_vma.c ++++ b/drivers/gpu/drm/i915/i915_vma.c +@@ -1870,12 +1870,13 @@ int _i915_vma_move_to_active(struct i915_vma *vma, + enum dma_resv_usage usage; + int idx; + +- obj->read_domains = 0; + if (flags & EXEC_OBJECT_WRITE) { + usage = DMA_RESV_USAGE_WRITE; + obj->write_domain = I915_GEM_DOMAIN_RENDER; ++ obj->read_domains = 0; + } else { + usage = DMA_RESV_USAGE_READ; ++ obj->write_domain = 0; + } + + dma_fence_array_for_each(curr, idx, fence) +diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c +index 8640a8a8a4691..44aa526294439 100644 +--- a/drivers/gpu/drm/meson/meson_plane.c ++++ b/drivers/gpu/drm/meson/meson_plane.c +@@ -168,7 +168,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane, + + /* Enable OSD and BLK0, set max global alpha */ + priv->viu.osd1_ctrl_stat = OSD_ENABLE | +- (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | ++ (0x100 << OSD_GLOBAL_ALPHA_SHIFT) | + OSD_BLK0_ENABLE; + + priv->viu.osd1_ctrl_stat2 = readl(priv->io_base + +diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c +index bb7e109534de1..d4b907889a21d 100644 +--- a/drivers/gpu/drm/meson/meson_viu.c ++++ b/drivers/gpu/drm/meson/meson_viu.c +@@ -94,7 +94,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv, + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); + writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); +- writel((m[11] & 0x1fff) << 16, ++ writel((m[11] & 0x1fff), + priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); + + writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), +diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c +index a189982601a48..e8040defe6073 100644 +--- a/drivers/gpu/drm/panel/panel-edp.c ++++ b/drivers/gpu/drm/panel/panel-edp.c +@@ -1270,7 +1270,8 @@ static const struct panel_desc innolux_n116bca_ea1 = { + }, + .delay = { + .hpd_absent = 200, +- .prepare_to_enable = 80, ++ .enable = 80, ++ .disable = 50, + .unprepare = 500, + }, + }; +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +index d6e831576cd2b..88271f04615b0 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +@@ -1436,11 +1436,15 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, + die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; + die |= RK3568_SYS_DSP_INFACE_EN_HDMI | + FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); ++ dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL; ++ dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags); + break; + case ROCKCHIP_VOP2_EP_EDP0: + die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; + die |= RK3568_SYS_DSP_INFACE_EN_EDP | + FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); ++ dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL; ++ dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags); + break; + case ROCKCHIP_VOP2_EP_MIPI0: + die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX; +diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c +index fc8c1420c0b69..64b14ac4c7b02 100644 +--- a/drivers/iommu/intel/dmar.c ++++ b/drivers/iommu/intel/dmar.c +@@ -2368,13 +2368,6 @@ static int dmar_device_hotplug(acpi_handle handle, bool insert) + if (!dmar_in_use()) + return 0; + +- /* +- * It's unlikely that any I/O board is hot added before the IOMMU +- * subsystem is initialized. +- */ +- if (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled) +- return -EOPNOTSUPP; +- + if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { + tmp = handle; + } else { +diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c +index c0464959cbcdb..861a239d905a4 100644 +--- a/drivers/iommu/intel/iommu.c ++++ b/drivers/iommu/intel/iommu.c +@@ -3133,7 +3133,13 @@ static int __init init_dmars(void) + + #ifdef CONFIG_INTEL_IOMMU_SVM + if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { ++ /* ++ * Call dmar_alloc_hwirq() with dmar_global_lock held, ++ * could cause possible lock race condition. ++ */ ++ up_write(&dmar_global_lock); + ret = intel_svm_enable_prq(iommu); ++ down_write(&dmar_global_lock); + if (ret) + goto free_iommu; + } +@@ -4039,6 +4045,7 @@ int __init intel_iommu_init(void) + force_on = (!intel_iommu_tboot_noforce && tboot_force_iommu()) || + platform_optin_force_iommu(); + ++ down_write(&dmar_global_lock); + if (dmar_table_init()) { + if (force_on) + panic("tboot: Failed to initialize DMAR table\n"); +@@ -4051,6 +4058,16 @@ int __init intel_iommu_init(void) + goto out_free_dmar; + } + ++ up_write(&dmar_global_lock); ++ ++ /* ++ * The bus notifier takes the dmar_global_lock, so lockdep will ++ * complain later when we register it under the lock. ++ */ ++ dmar_register_bus_notifier(); ++ ++ down_write(&dmar_global_lock); ++ + if (!no_iommu) + intel_iommu_debugfs_init(); + +@@ -4098,9 +4115,11 @@ int __init intel_iommu_init(void) + pr_err("Initialization failed\n"); + goto out_free_dmar; + } ++ up_write(&dmar_global_lock); + + init_iommu_pm_ops(); + ++ down_read(&dmar_global_lock); + for_each_active_iommu(iommu, drhd) { + /* + * The flush queue implementation does not perform +@@ -4118,11 +4137,13 @@ int __init intel_iommu_init(void) + "%s", iommu->name); + iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); + } ++ up_read(&dmar_global_lock); + + bus_set_iommu(&pci_bus_type, &intel_iommu_ops); + if (si_domain && !hw_pass_through) + register_memory_notifier(&intel_iommu_memory_nb); + ++ down_read(&dmar_global_lock); + if (probe_acpi_namespace_devices()) + pr_warn("ACPI name space devices didn't probe correctly\n"); + +@@ -4133,15 +4154,17 @@ int __init intel_iommu_init(void) + + iommu_disable_protect_mem_regions(iommu); + } ++ up_read(&dmar_global_lock); + +- intel_iommu_enabled = 1; +- dmar_register_bus_notifier(); + pr_info("Intel(R) Virtualization Technology for Directed I/O\n"); + ++ intel_iommu_enabled = 1; ++ + return 0; + + out_free_dmar: + intel_iommu_free_dmars(); ++ up_write(&dmar_global_lock); + return ret; + } + +diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c +index 520ed965bb7a4..583ca847a39cb 100644 +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -314,7 +314,7 @@ static int unflatten_dt_nodes(const void *blob, + for (offset = 0; + offset >= 0 && depth >= initial_depth; + offset = fdt_next_node(blob, offset, &depth)) { +- if (WARN_ON_ONCE(depth >= FDT_MAX_DEPTH)) ++ if (WARN_ON_ONCE(depth >= FDT_MAX_DEPTH - 1)) + continue; + + if (!IS_ENABLED(CONFIG_OF_KOBJ) && +diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c +index f69ab90b5e22d..6052f264bbb0a 100644 +--- a/drivers/parisc/ccio-dma.c ++++ b/drivers/parisc/ccio-dma.c +@@ -1546,6 +1546,7 @@ static int __init ccio_probe(struct parisc_device *dev) + } + ccio_ioc_init(ioc); + if (ccio_init_resources(ioc)) { ++ iounmap(ioc->ioc_regs); + kfree(ioc); + return -ENOMEM; + } +diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c +index 6bec7f1431348..704a99d2f93ce 100644 +--- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c ++++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c +@@ -530,10 +530,10 @@ DECLARE_MSM_GPIO_PINS(187); + DECLARE_MSM_GPIO_PINS(188); + DECLARE_MSM_GPIO_PINS(189); + +-static const unsigned int sdc2_clk_pins[] = { 190 }; +-static const unsigned int sdc2_cmd_pins[] = { 191 }; +-static const unsigned int sdc2_data_pins[] = { 192 }; +-static const unsigned int ufs_reset_pins[] = { 193 }; ++static const unsigned int ufs_reset_pins[] = { 190 }; ++static const unsigned int sdc2_clk_pins[] = { 191 }; ++static const unsigned int sdc2_cmd_pins[] = { 192 }; ++static const unsigned int sdc2_data_pins[] = { 193 }; + + enum sc8180x_functions { + msm_mux_adsp_ext, +@@ -1582,7 +1582,7 @@ static const int sc8180x_acpi_reserved_gpios[] = { + static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = { + { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 }, + { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 }, +- { 37, 43 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 }, ++ { 37, 44 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 }, + { 42, 48 }, { 46, 50 }, { 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 }, + { 51, 116 }, { 51, 123 }, { 53, 54 }, { 54, 55 }, { 55, 56 }, + { 56, 57 }, { 58, 58 }, { 60, 60 }, { 68, 62 }, { 70, 63 }, { 76, 86 }, +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c +index 21054fcacd345..18088f6f44b23 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c +@@ -98,7 +98,7 @@ MODULE_DEVICE_TABLE(of, a100_r_pinctrl_match); + static struct platform_driver a100_r_pinctrl_driver = { + .probe = a100_r_pinctrl_probe, + .driver = { +- .name = "sun50iw10p1-r-pinctrl", ++ .name = "sun50i-a100-r-pinctrl", + .of_match_table = a100_r_pinctrl_match, + }, + }; +diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c +index 386bb523c69ea..bdc3efdb12219 100644 +--- a/fs/cifs/connect.c ++++ b/fs/cifs/connect.c +@@ -707,9 +707,6 @@ cifs_readv_from_socket(struct TCP_Server_Info *server, struct msghdr *smb_msg) + int length = 0; + int total_read; + +- smb_msg->msg_control = NULL; +- smb_msg->msg_controllen = 0; +- + for (total_read = 0; msg_data_left(smb_msg); total_read += length) { + try_to_freeze(); + +@@ -765,7 +762,7 @@ int + cifs_read_from_socket(struct TCP_Server_Info *server, char *buf, + unsigned int to_read) + { +- struct msghdr smb_msg; ++ struct msghdr smb_msg = {}; + struct kvec iov = {.iov_base = buf, .iov_len = to_read}; + iov_iter_kvec(&smb_msg.msg_iter, READ, &iov, 1, to_read); + +@@ -775,15 +772,13 @@ cifs_read_from_socket(struct TCP_Server_Info *server, char *buf, + ssize_t + cifs_discard_from_socket(struct TCP_Server_Info *server, size_t to_read) + { +- struct msghdr smb_msg; ++ struct msghdr smb_msg = {}; + + /* + * iov_iter_discard already sets smb_msg.type and count and iov_offset + * and cifs_readv_from_socket sets msg_control and msg_controllen + * so little to initialize in struct msghdr + */ +- smb_msg.msg_name = NULL; +- smb_msg.msg_namelen = 0; + iov_iter_discard(&smb_msg.msg_iter, READ, to_read); + + return cifs_readv_from_socket(server, &smb_msg); +@@ -793,7 +788,7 @@ int + cifs_read_page_from_socket(struct TCP_Server_Info *server, struct page *page, + unsigned int page_offset, unsigned int to_read) + { +- struct msghdr smb_msg; ++ struct msghdr smb_msg = {}; + struct bio_vec bv = { + .bv_page = page, .bv_len = to_read, .bv_offset = page_offset}; + iov_iter_bvec(&smb_msg.msg_iter, READ, &bv, 1, to_read); +diff --git a/fs/cifs/file.c b/fs/cifs/file.c +index 0f03c0bfdf280..02dd591acabb3 100644 +--- a/fs/cifs/file.c ++++ b/fs/cifs/file.c +@@ -3327,6 +3327,9 @@ static ssize_t __cifs_writev( + + ssize_t cifs_direct_writev(struct kiocb *iocb, struct iov_iter *from) + { ++ struct file *file = iocb->ki_filp; ++ ++ cifs_revalidate_mapping(file->f_inode); + return __cifs_writev(iocb, from, true); + } + +diff --git a/fs/cifs/transport.c b/fs/cifs/transport.c +index bfc9bd55870a0..8adc0f2a59518 100644 +--- a/fs/cifs/transport.c ++++ b/fs/cifs/transport.c +@@ -196,10 +196,6 @@ smb_send_kvec(struct TCP_Server_Info *server, struct msghdr *smb_msg, + + *sent = 0; + +- smb_msg->msg_name = (struct sockaddr *) &server->dstaddr; +- smb_msg->msg_namelen = sizeof(struct sockaddr); +- smb_msg->msg_control = NULL; +- smb_msg->msg_controllen = 0; + if (server->noblocksnd) + smb_msg->msg_flags = MSG_DONTWAIT + MSG_NOSIGNAL; + else +@@ -311,7 +307,7 @@ __smb_send_rqst(struct TCP_Server_Info *server, int num_rqst, + sigset_t mask, oldmask; + size_t total_len = 0, sent, size; + struct socket *ssocket = server->ssocket; +- struct msghdr smb_msg; ++ struct msghdr smb_msg = {}; + __be32 rfc1002_marker; + + if (cifs_rdma_enabled(server)) { +diff --git a/fs/nfs/internal.h b/fs/nfs/internal.h +index 8f8cd6e2d4dbc..597e3ce3f148a 100644 +--- a/fs/nfs/internal.h ++++ b/fs/nfs/internal.h +@@ -604,6 +604,31 @@ static inline gfp_t nfs_io_gfp_mask(void) + return GFP_KERNEL; + } + ++/* ++ * Special version of should_remove_suid() that ignores capabilities. ++ */ ++static inline int nfs_should_remove_suid(const struct inode *inode) ++{ ++ umode_t mode = inode->i_mode; ++ int kill = 0; ++ ++ /* suid always must be killed */ ++ if (unlikely(mode & S_ISUID)) ++ kill = ATTR_KILL_SUID; ++ ++ /* ++ * sgid without any exec bits is just a mandatory locking mark; leave ++ * it alone. If some exec bits are set, it's a real sgid; kill it. ++ */ ++ if (unlikely((mode & S_ISGID) && (mode & S_IXGRP))) ++ kill |= ATTR_KILL_SGID; ++ ++ if (unlikely(kill && S_ISREG(mode))) ++ return kill; ++ ++ return 0; ++} ++ + /* unlink.c */ + extern struct rpc_task * + nfs_async_rename(struct inode *old_dir, struct inode *new_dir, +diff --git a/fs/nfs/nfs42proc.c b/fs/nfs/nfs42proc.c +index 068c45b3bc1ab..6dab9e4083729 100644 +--- a/fs/nfs/nfs42proc.c ++++ b/fs/nfs/nfs42proc.c +@@ -78,10 +78,15 @@ static int _nfs42_proc_fallocate(struct rpc_message *msg, struct file *filep, + + status = nfs4_call_sync(server->client, server, msg, + &args.seq_args, &res.seq_res, 0); +- if (status == 0) ++ if (status == 0) { ++ if (nfs_should_remove_suid(inode)) { ++ spin_lock(&inode->i_lock); ++ nfs_set_cache_invalid(inode, NFS_INO_INVALID_MODE); ++ spin_unlock(&inode->i_lock); ++ } + status = nfs_post_op_update_inode_force_wcc(inode, + res.falloc_fattr); +- ++ } + if (msg->rpc_proc == &nfs4_procedures[NFSPROC4_CLNT_ALLOCATE]) + trace_nfs4_fallocate(inode, &args, status); + else +diff --git a/fs/nfs/super.c b/fs/nfs/super.c +index 6ab5eeb000dc0..5e4bacb77bfc7 100644 +--- a/fs/nfs/super.c ++++ b/fs/nfs/super.c +@@ -1051,22 +1051,31 @@ static void nfs_fill_super(struct super_block *sb, struct nfs_fs_context *ctx) + if (ctx->bsize) + sb->s_blocksize = nfs_block_size(ctx->bsize, &sb->s_blocksize_bits); + +- if (server->nfs_client->rpc_ops->version != 2) { +- /* The VFS shouldn't apply the umask to mode bits. We will do +- * so ourselves when necessary. ++ switch (server->nfs_client->rpc_ops->version) { ++ case 2: ++ sb->s_time_gran = 1000; ++ sb->s_time_min = 0; ++ sb->s_time_max = U32_MAX; ++ break; ++ case 3: ++ /* ++ * The VFS shouldn't apply the umask to mode bits. ++ * We will do so ourselves when necessary. + */ + sb->s_flags |= SB_POSIXACL; + sb->s_time_gran = 1; +- sb->s_export_op = &nfs_export_ops; +- } else +- sb->s_time_gran = 1000; +- +- if (server->nfs_client->rpc_ops->version != 4) { + sb->s_time_min = 0; + sb->s_time_max = U32_MAX; +- } else { ++ sb->s_export_op = &nfs_export_ops; ++ break; ++ case 4: ++ sb->s_flags |= SB_POSIXACL; ++ sb->s_time_gran = 1; + sb->s_time_min = S64_MIN; + sb->s_time_max = S64_MAX; ++ if (server->caps & NFS_CAP_ATOMIC_OPEN_V1) ++ sb->s_export_op = &nfs_export_ops; ++ break; + } + + sb->s_magic = NFS_SUPER_MAGIC; +diff --git a/fs/nfs/write.c b/fs/nfs/write.c +index 5d7e1c2061842..4212473c69ee9 100644 +--- a/fs/nfs/write.c ++++ b/fs/nfs/write.c +@@ -1497,31 +1497,6 @@ void nfs_commit_prepare(struct rpc_task *task, void *calldata) + NFS_PROTO(data->inode)->commit_rpc_prepare(task, data); + } + +-/* +- * Special version of should_remove_suid() that ignores capabilities. +- */ +-static int nfs_should_remove_suid(const struct inode *inode) +-{ +- umode_t mode = inode->i_mode; +- int kill = 0; +- +- /* suid always must be killed */ +- if (unlikely(mode & S_ISUID)) +- kill = ATTR_KILL_SUID; +- +- /* +- * sgid without any exec bits is just a mandatory locking mark; leave +- * it alone. If some exec bits are set, it's a real sgid; kill it. +- */ +- if (unlikely((mode & S_ISGID) && (mode & S_IXGRP))) +- kill |= ATTR_KILL_SGID; +- +- if (unlikely(kill && S_ISREG(mode))) +- return kill; +- +- return 0; +-} +- + static void nfs_writeback_check_extend(struct nfs_pgio_header *hdr, + struct nfs_fattr *fattr) + { +diff --git a/include/linux/dmar.h b/include/linux/dmar.h +index f3a3d95df5325..cbd714a198a0a 100644 +--- a/include/linux/dmar.h ++++ b/include/linux/dmar.h +@@ -69,7 +69,6 @@ struct dmar_pci_notify_info { + + extern struct rw_semaphore dmar_global_lock; + extern struct list_head dmar_drhd_units; +-extern int intel_iommu_enabled; + + #define for_each_drhd_unit(drhd) \ + list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ +@@ -93,8 +92,7 @@ extern int intel_iommu_enabled; + static inline bool dmar_rcu_check(void) + { + return rwsem_is_locked(&dmar_global_lock) || +- system_state == SYSTEM_BOOTING || +- (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled); ++ system_state == SYSTEM_BOOTING; + } + + #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) +diff --git a/include/linux/of_device.h b/include/linux/of_device.h +index 1d7992a02e36e..1a803e4335d30 100644 +--- a/include/linux/of_device.h ++++ b/include/linux/of_device.h +@@ -101,8 +101,9 @@ static inline struct device_node *of_cpu_device_node_get(int cpu) + } + + static inline int of_dma_configure_id(struct device *dev, +- struct device_node *np, +- bool force_dma) ++ struct device_node *np, ++ bool force_dma, ++ const u32 *id) + { + return 0; + } +diff --git a/include/net/xfrm.h b/include/net/xfrm.h +index c39d910d4b454..9ca397eed1638 100644 +--- a/include/net/xfrm.h ++++ b/include/net/xfrm.h +@@ -1195,6 +1195,8 @@ int __xfrm_sk_clone_policy(struct sock *sk, const struct sock *osk); + + static inline int xfrm_sk_clone_policy(struct sock *sk, const struct sock *osk) + { ++ if (!sk_fullsock(osk)) ++ return 0; + sk->sk_policy[0] = NULL; + sk->sk_policy[1] = NULL; + if (unlikely(osk->sk_policy[0] || osk->sk_policy[1])) +diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c +index 48833d0edd089..602da2cfd57c8 100644 +--- a/io_uring/io_uring.c ++++ b/io_uring/io_uring.c +@@ -5061,7 +5061,8 @@ done: + req_set_fail(req); + __io_req_complete(req, issue_flags, ret, 0); + /* put file to avoid an attempt to IOPOLL the req */ +- io_put_file(req->file); ++ if (!(req->flags & REQ_F_FIXED_FILE)) ++ io_put_file(req->file); + req->file = NULL; + return 0; + } +diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c +index afc6c0e9c966e..f93983910b5e1 100644 +--- a/kernel/cgroup/cgroup-v1.c ++++ b/kernel/cgroup/cgroup-v1.c +@@ -59,6 +59,7 @@ int cgroup_attach_task_all(struct task_struct *from, struct task_struct *tsk) + int retval = 0; + + mutex_lock(&cgroup_mutex); ++ cpus_read_lock(); + percpu_down_write(&cgroup_threadgroup_rwsem); + for_each_root(root) { + struct cgroup *from_cgrp; +@@ -72,6 +73,7 @@ int cgroup_attach_task_all(struct task_struct *from, struct task_struct *tsk) + break; + } + percpu_up_write(&cgroup_threadgroup_rwsem); ++ cpus_read_unlock(); + mutex_unlock(&cgroup_mutex); + + return retval; +diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c +index da8b3cc67234d..028eb28c7882d 100644 +--- a/net/ipv4/ip_output.c ++++ b/net/ipv4/ip_output.c +@@ -1704,7 +1704,7 @@ void ip_send_unicast_reply(struct sock *sk, struct sk_buff *skb, + tcp_hdr(skb)->source, tcp_hdr(skb)->dest, + arg->uid); + security_skb_classify_flow(skb, flowi4_to_flowi_common(&fl4)); +- rt = ip_route_output_key(net, &fl4); ++ rt = ip_route_output_flow(net, &fl4, sk); + if (IS_ERR(rt)) + return; + +diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c +index 586c102ce152d..9fd92e263d0a3 100644 +--- a/net/ipv4/tcp_ipv4.c ++++ b/net/ipv4/tcp_ipv4.c +@@ -819,6 +819,7 @@ static void tcp_v4_send_reset(const struct sock *sk, struct sk_buff *skb) + ctl_sk->sk_priority = (sk->sk_state == TCP_TIME_WAIT) ? + inet_twsk(sk)->tw_priority : sk->sk_priority; + transmit_time = tcp_transmit_time(sk); ++ xfrm_sk_clone_policy(ctl_sk, sk); + } + ip_send_unicast_reply(ctl_sk, + skb, &TCP_SKB_CB(skb)->header.h4.opt, +@@ -827,6 +828,7 @@ static void tcp_v4_send_reset(const struct sock *sk, struct sk_buff *skb) + transmit_time); + + ctl_sk->sk_mark = 0; ++ xfrm_sk_free_policy(ctl_sk); + sock_net_set(ctl_sk, &init_net); + __TCP_INC_STATS(net, TCP_MIB_OUTSEGS); + __TCP_INC_STATS(net, TCP_MIB_OUTRSTS); +diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c +index be09941fe6d9a..5eabe746cfa76 100644 +--- a/net/ipv6/tcp_ipv6.c ++++ b/net/ipv6/tcp_ipv6.c +@@ -952,7 +952,10 @@ static void tcp_v6_send_response(const struct sock *sk, struct sk_buff *skb, u32 + * Underlying function will use this to retrieve the network + * namespace + */ +- dst = ip6_dst_lookup_flow(sock_net(ctl_sk), ctl_sk, &fl6, NULL); ++ if (sk && sk->sk_state != TCP_TIME_WAIT) ++ dst = ip6_dst_lookup_flow(net, sk, &fl6, NULL); /*sk's xfrm_policy can be referred*/ ++ else ++ dst = ip6_dst_lookup_flow(net, ctl_sk, &fl6, NULL); + if (!IS_ERR(dst)) { + skb_dst_set(buff, dst); + ip6_xmit(ctl_sk, buff, &fl6, fl6.flowi6_mark, NULL, +diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c +index c1a01947530f0..db8c0de1de422 100644 +--- a/net/sunrpc/clnt.c ++++ b/net/sunrpc/clnt.c +@@ -2858,6 +2858,9 @@ int rpc_clnt_test_and_add_xprt(struct rpc_clnt *clnt, + + task = rpc_call_null_helper(clnt, xprt, NULL, RPC_TASK_ASYNC, + &rpc_cb_add_xprt_call_ops, data); ++ if (IS_ERR(task)) ++ return PTR_ERR(task); ++ + data->xps->xps_nunique_destaddr_xprts++; + rpc_put_task(task); + success: +diff --git a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c +index 53b024cea3b3e..5ecafffe7ce59 100644 +--- a/net/sunrpc/xprt.c ++++ b/net/sunrpc/xprt.c +@@ -1179,11 +1179,8 @@ xprt_request_dequeue_receive_locked(struct rpc_task *task) + { + struct rpc_rqst *req = task->tk_rqstp; + +- if (test_and_clear_bit(RPC_TASK_NEED_RECV, &task->tk_runstate)) { ++ if (test_and_clear_bit(RPC_TASK_NEED_RECV, &task->tk_runstate)) + xprt_request_rb_remove(req->rq_xprt, req); +- xdr_free_bvec(&req->rq_rcv_buf); +- req->rq_private_buf.bvec = NULL; +- } + } + + /** +@@ -1221,6 +1218,8 @@ void xprt_complete_rqst(struct rpc_task *task, int copied) + + xprt->stat.recvs++; + ++ xdr_free_bvec(&req->rq_rcv_buf); ++ req->rq_private_buf.bvec = NULL; + req->rq_private_buf.len = copied; + /* Ensure all writes are done before we update */ + /* req->rq_reply_bytes_recvd */ +@@ -1453,6 +1452,7 @@ xprt_request_dequeue_xprt(struct rpc_task *task) + xprt_request_dequeue_transmit_locked(task); + xprt_request_dequeue_receive_locked(task); + spin_unlock(&xprt->queue_lock); ++ xdr_free_bvec(&req->rq_rcv_buf); + } + } + +diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c +index 61df4d33c48ff..7f340f18599c9 100644 +--- a/sound/pci/hda/patch_sigmatel.c ++++ b/sound/pci/hda/patch_sigmatel.c +@@ -209,6 +209,7 @@ struct sigmatel_spec { + + /* beep widgets */ + hda_nid_t anabeep_nid; ++ bool beep_power_on; + + /* SPDIF-out mux */ + const char * const *spdif_labels; +@@ -4443,6 +4444,28 @@ static int stac_suspend(struct hda_codec *codec) + + return 0; + } ++ ++static int stac_check_power_status(struct hda_codec *codec, hda_nid_t nid) ++{ ++#ifdef CONFIG_SND_HDA_INPUT_BEEP ++ struct sigmatel_spec *spec = codec->spec; ++#endif ++ int ret = snd_hda_gen_check_power_status(codec, nid); ++ ++#ifdef CONFIG_SND_HDA_INPUT_BEEP ++ if (nid == spec->gen.beep_nid && codec->beep) { ++ if (codec->beep->enabled != spec->beep_power_on) { ++ spec->beep_power_on = codec->beep->enabled; ++ if (spec->beep_power_on) ++ snd_hda_power_up_pm(codec); ++ else ++ snd_hda_power_down_pm(codec); ++ } ++ ret |= spec->beep_power_on; ++ } ++#endif ++ return ret; ++} + #else + #define stac_suspend NULL + #endif /* CONFIG_PM */ +@@ -4455,6 +4478,7 @@ static const struct hda_codec_ops stac_patch_ops = { + .unsol_event = snd_hda_jack_unsol_event, + #ifdef CONFIG_PM + .suspend = stac_suspend, ++ .check_power_status = stac_check_power_status, + #endif + }; + +diff --git a/tools/include/uapi/asm/errno.h b/tools/include/uapi/asm/errno.h +index d30439b4b8ab4..869379f91fe48 100644 +--- a/tools/include/uapi/asm/errno.h ++++ b/tools/include/uapi/asm/errno.h +@@ -9,8 +9,8 @@ + #include "../../../arch/alpha/include/uapi/asm/errno.h" + #elif defined(__mips__) + #include "../../../arch/mips/include/uapi/asm/errno.h" +-#elif defined(__xtensa__) +-#include "../../../arch/xtensa/include/uapi/asm/errno.h" ++#elif defined(__hppa__) ++#include "../../../arch/parisc/include/uapi/asm/errno.h" + #else + #include <asm-generic/errno.h> + #endif
