commit: 3dbd32d6f07aec079dccc14cdf4aad43a43c8bf9 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Wed Oct 12 11:17:17 2022 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Wed Oct 12 11:17:17 2022 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=3dbd32d6
Linux patch 5.19.15 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> 0000_README | 4 + 1014_linux-5.19.15.patch | 2578 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 2582 insertions(+) diff --git a/0000_README b/0000_README index df106d7b..5d6628ec 100644 --- a/0000_README +++ b/0000_README @@ -99,6 +99,10 @@ Patch: 1013_linux-5.19.14.patch From: http://www.kernel.org Desc: Linux 5.19.14 +Patch: 1014_linux-5.19.15.patch +From: http://www.kernel.org +Desc: Linux 5.19.15 + Patch: 1500_XATTR_USER_PREFIX.patch From: https://bugs.gentoo.org/show_bug.cgi?id=470644 Desc: Support for namespace user.pax.* on tmpfs. diff --git a/1014_linux-5.19.15.patch b/1014_linux-5.19.15.patch new file mode 100644 index 00000000..d5600ea4 --- /dev/null +++ b/1014_linux-5.19.15.patch @@ -0,0 +1,2578 @@ +diff --git a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt +index 8a9f3559335b5..7e14e26676ec9 100644 +--- a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt ++++ b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt +@@ -34,8 +34,8 @@ Example: + Use specific request line passing from dma + For example, MMC request line is 5 + +- sdhci: sdhci@98e00000 { +- compatible = "moxa,moxart-sdhci"; ++ mmc: mmc@98e00000 { ++ compatible = "moxa,moxart-mmc"; + reg = <0x98e00000 0x5C>; + interrupts = <5 0>; + clocks = <&clk_apb>; +diff --git a/Documentation/process/code-of-conduct-interpretation.rst b/Documentation/process/code-of-conduct-interpretation.rst +index e899f14a4ba24..4f8a06b00f608 100644 +--- a/Documentation/process/code-of-conduct-interpretation.rst ++++ b/Documentation/process/code-of-conduct-interpretation.rst +@@ -51,7 +51,7 @@ the Technical Advisory Board (TAB) or other maintainers if you're + uncertain how to handle situations that come up. It will not be + considered a violation report unless you want it to be. If you are + uncertain about approaching the TAB or any other maintainers, please +-reach out to our conflict mediator, Mishi Choudhary <[email protected]>. ++reach out to our conflict mediator, Joanna Lee <[email protected]>. + + In the end, "be kind to each other" is really what the end goal is for + everybody. We know everyone is human and we all fail at times, but the +diff --git a/Makefile b/Makefile +index ff4a158671455..af05237987ef3 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + VERSION = 5 + PATCHLEVEL = 19 +-SUBLEVEL = 14 ++SUBLEVEL = 15 + EXTRAVERSION = + NAME = Superb Owl + +@@ -830,8 +830,8 @@ endif + # Initialize all stack variables with a zero value. + ifdef CONFIG_INIT_STACK_ALL_ZERO + KBUILD_CFLAGS += -ftrivial-auto-var-init=zero +-ifdef CONFIG_CC_IS_CLANG +-# https://bugs.llvm.org/show_bug.cgi?id=45497 ++ifdef CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_ENABLER ++# https://github.com/llvm/llvm-project/issues/44842 + KBUILD_CFLAGS += -enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang + endif + endif +diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts +index eb5291b0ee3aa..e07b807b4cec5 100644 +--- a/arch/arm/boot/dts/moxart-uc7112lx.dts ++++ b/arch/arm/boot/dts/moxart-uc7112lx.dts +@@ -79,7 +79,7 @@ + clocks = <&ref12>; + }; + +-&sdhci { ++&mmc { + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi +index f5f070a874823..764832ddfa78a 100644 +--- a/arch/arm/boot/dts/moxart.dtsi ++++ b/arch/arm/boot/dts/moxart.dtsi +@@ -93,8 +93,8 @@ + clock-names = "PCLK"; + }; + +- sdhci: sdhci@98e00000 { +- compatible = "moxa,moxart-sdhci"; ++ mmc: mmc@98e00000 { ++ compatible = "moxa,moxart-mmc"; + reg = <0x98e00000 0x5C>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_apb>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +index 40cf2236c0b61..ca48d9a54939c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -558,7 +558,7 @@ + }; + + &usb_host0_xhci { +- extcon = <&usb2phy0>; ++ dr_mode = "host"; + status = "okay"; + }; + +diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c +index 227ed00093543..0e82bf85e59b3 100644 +--- a/arch/s390/kvm/gaccess.c ++++ b/arch/s390/kvm/gaccess.c +@@ -489,6 +489,8 @@ enum prot_type { + PROT_TYPE_ALC = 2, + PROT_TYPE_DAT = 3, + PROT_TYPE_IEP = 4, ++ /* Dummy value for passing an initialized value when code != PGM_PROTECTION */ ++ PROT_NONE, + }; + + static int trans_exc_ending(struct kvm_vcpu *vcpu, int code, unsigned long gva, u8 ar, +@@ -504,6 +506,10 @@ static int trans_exc_ending(struct kvm_vcpu *vcpu, int code, unsigned long gva, + switch (code) { + case PGM_PROTECTION: + switch (prot) { ++ case PROT_NONE: ++ /* We should never get here, acts like termination */ ++ WARN_ON_ONCE(1); ++ break; + case PROT_TYPE_IEP: + tec->b61 = 1; + fallthrough; +@@ -968,8 +974,10 @@ static int guest_range_to_gpas(struct kvm_vcpu *vcpu, unsigned long ga, u8 ar, + return rc; + } else { + gpa = kvm_s390_real_to_abs(vcpu, ga); +- if (kvm_is_error_gpa(vcpu->kvm, gpa)) ++ if (kvm_is_error_gpa(vcpu->kvm, gpa)) { + rc = PGM_ADDRESSING; ++ prot = PROT_NONE; ++ } + } + if (rc) + return trans_exc(vcpu, rc, ga, ar, mode, prot); +@@ -1112,8 +1120,6 @@ int access_guest_with_key(struct kvm_vcpu *vcpu, unsigned long ga, u8 ar, + if (rc == PGM_PROTECTION && try_storage_prot_override) + rc = access_guest_page_with_key(vcpu->kvm, mode, gpas[idx], + data, fragment_len, PAGE_SPO_ACC); +- if (rc == PGM_PROTECTION) +- prot = PROT_TYPE_KEYC; + if (rc) + break; + len -= fragment_len; +@@ -1123,6 +1129,10 @@ int access_guest_with_key(struct kvm_vcpu *vcpu, unsigned long ga, u8 ar, + if (rc > 0) { + bool terminate = (mode == GACC_STORE) && (idx > 0); + ++ if (rc == PGM_PROTECTION) ++ prot = PROT_TYPE_KEYC; ++ else ++ prot = PROT_NONE; + rc = trans_exc_ending(vcpu, rc, ga, ar, mode, prot, terminate); + } + out_unlock: +diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h +index 856081761b0fc..2cf7971d7f6c9 100644 +--- a/arch/sparc/include/asm/smp_32.h ++++ b/arch/sparc/include/asm/smp_32.h +@@ -33,9 +33,6 @@ extern volatile unsigned long cpu_callin_map[NR_CPUS]; + extern cpumask_t smp_commenced_mask; + extern struct linux_prom_registers smp_penguin_ctable; + +-typedef void (*smpfunc_t)(unsigned long, unsigned long, unsigned long, +- unsigned long, unsigned long); +- + void cpu_panic(void); + + /* +@@ -57,7 +54,7 @@ void smp_bogo(struct seq_file *); + void smp_info(struct seq_file *); + + struct sparc32_ipi_ops { +- void (*cross_call)(smpfunc_t func, cpumask_t mask, unsigned long arg1, ++ void (*cross_call)(void *func, cpumask_t mask, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4); + void (*resched)(int cpu); +@@ -66,28 +63,28 @@ struct sparc32_ipi_ops { + }; + extern const struct sparc32_ipi_ops *sparc32_ipi_ops; + +-static inline void xc0(smpfunc_t func) ++static inline void xc0(void *func) + { + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, 0, 0, 0, 0); + } + +-static inline void xc1(smpfunc_t func, unsigned long arg1) ++static inline void xc1(void *func, unsigned long arg1) + { + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, 0, 0, 0); + } +-static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2) ++static inline void xc2(void *func, unsigned long arg1, unsigned long arg2) + { + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, arg2, 0, 0); + } + +-static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2, ++static inline void xc3(void *func, unsigned long arg1, unsigned long arg2, + unsigned long arg3) + { + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, + arg1, arg2, arg3, 0); + } + +-static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2, ++static inline void xc4(void *func, unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4) + { + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, +diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c +index 1eed26d423fb2..991e9ad3d3e8f 100644 +--- a/arch/sparc/kernel/leon_smp.c ++++ b/arch/sparc/kernel/leon_smp.c +@@ -359,7 +359,7 @@ void leonsmp_ipi_interrupt(void) + } + + static struct smp_funcall { +- smpfunc_t func; ++ void *func; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; +@@ -372,7 +372,7 @@ static struct smp_funcall { + static DEFINE_SPINLOCK(cross_call_lock); + + /* Cross calls must be serialized, at least currently. */ +-static void leon_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, ++static void leon_cross_call(void *func, cpumask_t mask, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4) + { +@@ -384,7 +384,7 @@ static void leon_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, + + { + /* If you make changes here, make sure gcc generates proper code... */ +- register smpfunc_t f asm("i0") = func; ++ register void *f asm("i0") = func; + register unsigned long a1 asm("i1") = arg1; + register unsigned long a2 asm("i2") = arg2; + register unsigned long a3 asm("i3") = arg3; +@@ -444,11 +444,13 @@ static void leon_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, + /* Running cross calls. */ + void leon_cross_call_irq(void) + { ++ void (*func)(unsigned long, unsigned long, unsigned long, unsigned long, ++ unsigned long) = ccall_info.func; + int i = smp_processor_id(); + + ccall_info.processors_in[i] = 1; +- ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, +- ccall_info.arg4, ccall_info.arg5); ++ func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4, ++ ccall_info.arg5); + ccall_info.processors_out[i] = 1; + } + +diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c +index ff30f03beb7c7..9a62a5cf33370 100644 +--- a/arch/sparc/kernel/sun4d_smp.c ++++ b/arch/sparc/kernel/sun4d_smp.c +@@ -268,7 +268,7 @@ static void sun4d_ipi_resched(int cpu) + } + + static struct smp_funcall { +- smpfunc_t func; ++ void *func; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; +@@ -281,7 +281,7 @@ static struct smp_funcall { + static DEFINE_SPINLOCK(cross_call_lock); + + /* Cross calls must be serialized, at least currently. */ +-static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, ++static void sun4d_cross_call(void *func, cpumask_t mask, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4) + { +@@ -296,7 +296,7 @@ static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, + * If you make changes here, make sure + * gcc generates proper code... + */ +- register smpfunc_t f asm("i0") = func; ++ register void *f asm("i0") = func; + register unsigned long a1 asm("i1") = arg1; + register unsigned long a2 asm("i2") = arg2; + register unsigned long a3 asm("i3") = arg3; +@@ -353,11 +353,13 @@ static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, + /* Running cross calls. */ + void smp4d_cross_call_irq(void) + { ++ void (*func)(unsigned long, unsigned long, unsigned long, unsigned long, ++ unsigned long) = ccall_info.func; + int i = hard_smp_processor_id(); + + ccall_info.processors_in[i] = 1; +- ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, +- ccall_info.arg4, ccall_info.arg5); ++ func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4, ++ ccall_info.arg5); + ccall_info.processors_out[i] = 1; + } + +diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c +index 228a6527082dc..056df034e79ee 100644 +--- a/arch/sparc/kernel/sun4m_smp.c ++++ b/arch/sparc/kernel/sun4m_smp.c +@@ -157,7 +157,7 @@ static void sun4m_ipi_mask_one(int cpu) + } + + static struct smp_funcall { +- smpfunc_t func; ++ void *func; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; +@@ -170,7 +170,7 @@ static struct smp_funcall { + static DEFINE_SPINLOCK(cross_call_lock); + + /* Cross calls must be serialized, at least currently. */ +-static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, ++static void sun4m_cross_call(void *func, cpumask_t mask, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4) + { +@@ -230,11 +230,13 @@ static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, + /* Running cross calls. */ + void smp4m_cross_call_irq(void) + { ++ void (*func)(unsigned long, unsigned long, unsigned long, unsigned long, ++ unsigned long) = ccall_info.func; + int i = smp_processor_id(); + + ccall_info.processors_in[i] = 1; +- ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, +- ccall_info.arg4, ccall_info.arg5); ++ func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4, ++ ccall_info.arg5); + ccall_info.processors_out[i] = 1; + } + +diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c +index a9aa6a92c7fee..13f027afc875c 100644 +--- a/arch/sparc/mm/srmmu.c ++++ b/arch/sparc/mm/srmmu.c +@@ -1636,19 +1636,19 @@ static void __init get_srmmu_type(void) + /* Local cross-calls. */ + static void smp_flush_page_for_dma(unsigned long page) + { +- xc1((smpfunc_t) local_ops->page_for_dma, page); ++ xc1(local_ops->page_for_dma, page); + local_ops->page_for_dma(page); + } + + static void smp_flush_cache_all(void) + { +- xc0((smpfunc_t) local_ops->cache_all); ++ xc0(local_ops->cache_all); + local_ops->cache_all(); + } + + static void smp_flush_tlb_all(void) + { +- xc0((smpfunc_t) local_ops->tlb_all); ++ xc0(local_ops->tlb_all); + local_ops->tlb_all(); + } + +@@ -1659,7 +1659,7 @@ static void smp_flush_cache_mm(struct mm_struct *mm) + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) +- xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm); ++ xc1(local_ops->cache_mm, (unsigned long)mm); + local_ops->cache_mm(mm); + } + } +@@ -1671,7 +1671,7 @@ static void smp_flush_tlb_mm(struct mm_struct *mm) + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) { +- xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm); ++ xc1(local_ops->tlb_mm, (unsigned long)mm); + if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm) + cpumask_copy(mm_cpumask(mm), + cpumask_of(smp_processor_id())); +@@ -1691,8 +1691,8 @@ static void smp_flush_cache_range(struct vm_area_struct *vma, + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) +- xc3((smpfunc_t) local_ops->cache_range, +- (unsigned long) vma, start, end); ++ xc3(local_ops->cache_range, (unsigned long)vma, start, ++ end); + local_ops->cache_range(vma, start, end); + } + } +@@ -1708,8 +1708,8 @@ static void smp_flush_tlb_range(struct vm_area_struct *vma, + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) +- xc3((smpfunc_t) local_ops->tlb_range, +- (unsigned long) vma, start, end); ++ xc3(local_ops->tlb_range, (unsigned long)vma, start, ++ end); + local_ops->tlb_range(vma, start, end); + } + } +@@ -1723,8 +1723,7 @@ static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) +- xc2((smpfunc_t) local_ops->cache_page, +- (unsigned long) vma, page); ++ xc2(local_ops->cache_page, (unsigned long)vma, page); + local_ops->cache_page(vma, page); + } + } +@@ -1738,8 +1737,7 @@ static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) +- xc2((smpfunc_t) local_ops->tlb_page, +- (unsigned long) vma, page); ++ xc2(local_ops->tlb_page, (unsigned long)vma, page); + local_ops->tlb_page(vma, page); + } + } +@@ -1753,7 +1751,7 @@ static void smp_flush_page_to_ram(unsigned long page) + * XXX This experiment failed, research further... -DaveM + */ + #if 1 +- xc1((smpfunc_t) local_ops->page_to_ram, page); ++ xc1(local_ops->page_to_ram, page); + #endif + local_ops->page_to_ram(page); + } +@@ -1764,8 +1762,7 @@ static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) +- xc2((smpfunc_t) local_ops->sig_insns, +- (unsigned long) mm, insn_addr); ++ xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr); + local_ops->sig_insns(mm, insn_addr); + } + +diff --git a/arch/um/Makefile b/arch/um/Makefile +index f2fe63bfd819f..f1d4d67157be0 100644 +--- a/arch/um/Makefile ++++ b/arch/um/Makefile +@@ -132,10 +132,18 @@ export LDS_ELF_FORMAT := $(ELF_FORMAT) + # The wrappers will select whether using "malloc" or the kernel allocator. + LINK_WRAPS = -Wl,--wrap,malloc -Wl,--wrap,free -Wl,--wrap,calloc + ++# Avoid binutils 2.39+ warnings by marking the stack non-executable and ++# ignorning warnings for the kallsyms sections. ++LDFLAGS_EXECSTACK = -z noexecstack ++ifeq ($(CONFIG_LD_IS_BFD),y) ++LDFLAGS_EXECSTACK += $(call ld-option,--no-warn-rwx-segments) ++endif ++ + LD_FLAGS_CMDLINE = $(foreach opt,$(KBUILD_LDFLAGS),-Wl,$(opt)) + + # Used by link-vmlinux.sh which has special support for um link + export CFLAGS_vmlinux := $(LINK-y) $(LINK_WRAPS) $(LD_FLAGS_CMDLINE) ++export LDFLAGS_vmlinux := $(LDFLAGS_EXECSTACK) + + # When cleaning we don't include .config, so we don't include + # TT or skas makefiles and don't clean skas_ptregs.h. +diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c +index bd8b988576097..8d6befb24b8ed 100644 +--- a/arch/x86/events/intel/core.c ++++ b/arch/x86/events/intel/core.c +@@ -2101,6 +2101,15 @@ static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { + EVENT_EXTRA_END + }; + ++EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); ++EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); ++ ++static struct attribute *grt_mem_attrs[] = { ++ EVENT_PTR(mem_ld_grt), ++ EVENT_PTR(mem_st_grt), ++ NULL ++}; ++ + static struct extra_reg intel_grt_extra_regs[] __read_mostly = { + /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), +@@ -5874,6 +5883,36 @@ __init int intel_pmu_init(void) + name = "Tremont"; + break; + ++ case INTEL_FAM6_ALDERLAKE_N: ++ x86_pmu.mid_ack = true; ++ memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, ++ sizeof(hw_cache_event_ids)); ++ memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, ++ sizeof(hw_cache_extra_regs)); ++ hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; ++ ++ x86_pmu.event_constraints = intel_slm_event_constraints; ++ x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints; ++ x86_pmu.extra_regs = intel_grt_extra_regs; ++ ++ x86_pmu.pebs_aliases = NULL; ++ x86_pmu.pebs_prec_dist = true; ++ x86_pmu.pebs_block = true; ++ x86_pmu.lbr_pt_coexist = true; ++ x86_pmu.flags |= PMU_FL_HAS_RSP_1; ++ x86_pmu.flags |= PMU_FL_INSTR_LATENCY; ++ ++ intel_pmu_pebs_data_source_grt(); ++ x86_pmu.pebs_latency_data = adl_latency_data_small; ++ x86_pmu.get_event_constraints = tnt_get_event_constraints; ++ x86_pmu.limit_period = spr_limit_period; ++ td_attr = tnt_events_attrs; ++ mem_attr = grt_mem_attrs; ++ extra_attr = nhm_format_attr; ++ pr_cont("Gracemont events, "); ++ name = "gracemont"; ++ break; ++ + case INTEL_FAM6_WESTMERE: + case INTEL_FAM6_WESTMERE_EP: + case INTEL_FAM6_WESTMERE_EX: +@@ -6216,7 +6255,6 @@ __init int intel_pmu_init(void) + + case INTEL_FAM6_ALDERLAKE: + case INTEL_FAM6_ALDERLAKE_L: +- case INTEL_FAM6_ALDERLAKE_N: + case INTEL_FAM6_RAPTORLAKE: + case INTEL_FAM6_RAPTORLAKE_P: + /* +diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c +index 9b48d957d2b3f..139204aea94e3 100644 +--- a/arch/x86/events/intel/ds.c ++++ b/arch/x86/events/intel/ds.c +@@ -110,13 +110,18 @@ void __init intel_pmu_pebs_data_source_skl(bool pmem) + __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source); + } + +-static void __init intel_pmu_pebs_data_source_grt(u64 *data_source) ++static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source) + { + data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); + data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); + data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); + } + ++void __init intel_pmu_pebs_data_source_grt(void) ++{ ++ __intel_pmu_pebs_data_source_grt(pebs_data_source); ++} ++ + void __init intel_pmu_pebs_data_source_adl(void) + { + u64 *data_source; +@@ -127,7 +132,7 @@ void __init intel_pmu_pebs_data_source_adl(void) + + data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); +- intel_pmu_pebs_data_source_grt(data_source); ++ __intel_pmu_pebs_data_source_grt(data_source); + } + + static u64 precise_store_data(u64 status) +diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h +index 821098aebf78c..84f6f947ddef5 100644 +--- a/arch/x86/events/perf_event.h ++++ b/arch/x86/events/perf_event.h +@@ -1513,6 +1513,8 @@ void intel_pmu_pebs_data_source_skl(bool pmem); + + void intel_pmu_pebs_data_source_adl(void); + ++void intel_pmu_pebs_data_source_grt(void); ++ + int intel_pmu_setup_lbr_filter(struct perf_event *event); + + void intel_pt_interrupt(void); +diff --git a/arch/x86/um/shared/sysdep/syscalls_32.h b/arch/x86/um/shared/sysdep/syscalls_32.h +index 68fd2cf526fd7..f6e9f84397e79 100644 +--- a/arch/x86/um/shared/sysdep/syscalls_32.h ++++ b/arch/x86/um/shared/sysdep/syscalls_32.h +@@ -6,10 +6,9 @@ + #include <asm/unistd.h> + #include <sysdep/ptrace.h> + +-typedef long syscall_handler_t(struct pt_regs); ++typedef long syscall_handler_t(struct syscall_args); + + extern syscall_handler_t *sys_call_table[]; + + #define EXECUTE_SYSCALL(syscall, regs) \ +- ((long (*)(struct syscall_args)) \ +- (*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs)) ++ ((*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs)) +diff --git a/arch/x86/um/tls_32.c b/arch/x86/um/tls_32.c +index ac8eee093f9cd..66162eafd8e8f 100644 +--- a/arch/x86/um/tls_32.c ++++ b/arch/x86/um/tls_32.c +@@ -65,9 +65,6 @@ static int get_free_idx(struct task_struct* task) + struct thread_struct *t = &task->thread; + int idx; + +- if (!t->arch.tls_array) +- return GDT_ENTRY_TLS_MIN; +- + for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++) + if (!t->arch.tls_array[idx].present) + return idx + GDT_ENTRY_TLS_MIN; +@@ -240,9 +237,6 @@ static int get_tls_entry(struct task_struct *task, struct user_desc *info, + { + struct thread_struct *t = &task->thread; + +- if (!t->arch.tls_array) +- goto clear; +- + if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX) + return -EINVAL; + +diff --git a/arch/x86/um/vdso/Makefile b/arch/x86/um/vdso/Makefile +index 5943387e3f357..5ca366e15c767 100644 +--- a/arch/x86/um/vdso/Makefile ++++ b/arch/x86/um/vdso/Makefile +@@ -62,7 +62,7 @@ quiet_cmd_vdso = VDSO $@ + -Wl,-T,$(filter %.lds,$^) $(filter %.o,$^) && \ + sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@' + +-VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv ++VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv -z noexecstack + GCOV_PROFILE := n + + # +diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c +index 868bc7af21b0b..d078e5d73ed94 100644 +--- a/drivers/clk/ti/clk-44xx.c ++++ b/drivers/clk/ti/clk-44xx.c +@@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = { + }; + + static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = { +- "abe-clkctrl:0018:26", ++ "abe_cm:clk:0018:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = { + }; + + static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = { +- "abe-clkctrl:0020:26", ++ "abe_cm:clk:0020:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = { + }; + + static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = { +- "abe-clkctrl:0028:26", ++ "abe_cm:clk:0028:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = + }; + + static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = { +- "abe-clkctrl:0030:26", ++ "abe_cm:clk:0030:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = + }; + + static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = { +- "abe-clkctrl:0038:26", ++ "abe_cm:clk:0038:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = + + static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = { + { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" }, +- { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" }, ++ { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, + { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, +- { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" }, +- { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" }, +- { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" }, +- { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" }, +- { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" }, +- { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" }, +- { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" }, +- { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" }, +- { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" }, +- { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" }, ++ { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, ++ { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" }, ++ { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, ++ { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, ++ { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, ++ { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" }, ++ { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, ++ { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, ++ { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, ++ { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, + { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, + }; +@@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = { + + static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = { + { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" }, +- { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" }, ++ { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" }, + { 0 }, + }; + +@@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = { +- { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" }, ++ { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" }, + { 0 }, + }; + +@@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = { + }; + + static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = { +- { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" }, ++ { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" }, + { 0 }, + }; + +@@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = { + }; + + static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = { +- "l3-init-clkctrl:0038:24", ++ "l3_init_cm:clk:0038:24", + NULL, + }; + + static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = { +- "l3-init-clkctrl:0038:25", ++ "l3_init_cm:clk:0038:25", + NULL, + }; + +@@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon + }; + + static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = { +- "l3-init-clkctrl:0040:24", ++ "l3_init_cm:clk:0040:24", + NULL, + }; + +@@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini + }; + + static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = { +- { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" }, +- { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" }, +- { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" }, ++ { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" }, ++ { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" }, ++ { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" }, + { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" }, + { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" }, + { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" }, + { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" }, +- { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" }, ++ { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" }, + { 0 }, + }; + +@@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = { + }; + + static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = { +- "l4-per-clkctrl:00c0:26", ++ "l4_per_cm:clk:00c0:26", + "pad_clks_ck", + NULL, + }; +@@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = { +- { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" }, +- { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" }, +- { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" }, +- { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" }, +- { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" }, +- { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" }, ++ { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" }, ++ { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" }, ++ { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" }, ++ { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" }, ++ { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" }, ++ { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" }, + { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" }, + { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" }, + { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" }, +@@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons + { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" }, +- { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" }, ++ { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" }, + { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, +- { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" }, ++ { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" }, + { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, +@@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon + { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" }, + { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" }, +- { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" }, ++ { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" }, + { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" }, + { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, +@@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = { + }; + + static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = { +- "emu-sys-clkctrl:0000:22", ++ "emu_sys_cm:clk:0000:22", + NULL, + }; + +@@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init + }; + + static const char * const omap4_stm_clk_div_ck_parents[] __initconst = { +- "emu-sys-clkctrl:0000:20", ++ "emu_sys_cm:clk:0000:20", + NULL, + }; + +@@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = { + * hwmod support. Once hwmod is removed, these can be removed + * also. + */ +- DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"), +- DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"), +- DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"), +- DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"), +- DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"), +- DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"), +- DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"), +- DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"), +- DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"), +- DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"), +- DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"), +- DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"), +- DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"), +- DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"), +- DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"), +- DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"), +- DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"), +- DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"), +- DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"), +- DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"), +- DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"), +- DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"), +- DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"), +- DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"), +- DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"), +- DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"), +- DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"), +- DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"), +- DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"), +- DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"), +- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), +- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), +- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), +- DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"), +- DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"), +- DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"), +- DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"), +- DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"), +- DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"), +- DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"), +- DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"), +- DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"), +- DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"), +- DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"), +- DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"), +- DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"), +- DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"), +- DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"), +- DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"), +- DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"), +- DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"), +- DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"), +- DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"), +- DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"), +- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"), +- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"), +- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"), +- DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"), +- DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"), +- DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"), ++ DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"), ++ DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"), ++ DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"), ++ DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"), ++ DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"), ++ DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"), ++ DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"), ++ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), ++ DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"), ++ DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"), ++ DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"), ++ DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"), ++ DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"), ++ DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"), ++ DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"), ++ DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"), ++ DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"), ++ DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"), ++ DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"), ++ DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"), ++ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"), ++ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"), ++ DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"), ++ DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"), ++ DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"), ++ DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"), ++ DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"), ++ DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"), ++ DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"), ++ DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"), ++ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), ++ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), ++ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), ++ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"), ++ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"), ++ DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"), ++ DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"), ++ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"), ++ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"), ++ DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"), ++ DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"), ++ DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"), ++ DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"), ++ DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"), ++ DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"), ++ DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"), ++ DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"), ++ DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"), ++ DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"), ++ DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"), ++ DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"), ++ DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"), ++ DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"), ++ DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"), ++ DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"), ++ DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"), ++ DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"), + { .node_name = NULL }, + }; + +diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c +index b4aff76eb3735..90e0a9ea63515 100644 +--- a/drivers/clk/ti/clk-54xx.c ++++ b/drivers/clk/ti/clk-54xx.c +@@ -50,7 +50,7 @@ static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = { + }; + + static const char * const omap5_dmic_gfclk_parents[] __initconst = { +- "abe-clkctrl:0018:26", ++ "abe_cm:clk:0018:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -70,7 +70,7 @@ static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { + }; + + static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { +- "abe-clkctrl:0028:26", ++ "abe_cm:clk:0028:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -83,7 +83,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = + }; + + static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { +- "abe-clkctrl:0030:26", ++ "abe_cm:clk:0030:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -96,7 +96,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = + }; + + static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { +- "abe-clkctrl:0038:26", ++ "abe_cm:clk:0038:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -136,16 +136,16 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = + + static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { + { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, +- { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" }, ++ { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, + { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, +- { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" }, +- { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" }, +- { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" }, +- { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" }, +- { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" }, +- { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" }, +- { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" }, +- { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" }, ++ { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, ++ { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, ++ { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, ++ { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, ++ { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, ++ { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, ++ { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, ++ { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, + { 0 }, + }; + +@@ -268,12 +268,12 @@ static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { + }; + + static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { +- { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" }, +- { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" }, +- { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" }, +- { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" }, +- { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" }, +- { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" }, ++ { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, ++ { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, ++ { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, ++ { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, ++ { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, ++ { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, + { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, +@@ -345,7 +345,7 @@ static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { +- { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" }, ++ { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, + { 0 }, + }; + +@@ -378,7 +378,7 @@ static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = { +- { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" }, ++ { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" }, + { 0 }, + }; + +@@ -389,7 +389,7 @@ static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { + }; + + static const char * const omap5_mmc1_fclk_parents[] __initconst = { +- "l3init-clkctrl:0008:24", ++ "l3init_cm:clk:0008:24", + NULL, + }; + +@@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { + }; + + static const char * const omap5_mmc2_fclk_parents[] __initconst = { +- "l3init-clkctrl:0010:24", ++ "l3init_cm:clk:0010:24", + NULL, + }; + +@@ -430,12 +430,12 @@ static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initcons + }; + + static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { +- "l3init-clkctrl:0038:24", ++ "l3init_cm:clk:0038:24", + NULL, + }; + + static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { +- "l3init-clkctrl:0038:25", ++ "l3init_cm:clk:0038:25", + NULL, + }; + +@@ -494,8 +494,8 @@ static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initcons + }; + + static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { +- { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" }, +- { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, ++ { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, ++ { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, + { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, + { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, +@@ -519,7 +519,7 @@ static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initcon + { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, +- { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" }, ++ { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, + { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, +@@ -549,58 +549,58 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { + static struct ti_dt_clk omap54xx_clks[] = { + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), +- DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"), +- DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"), +- DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"), +- DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"), +- DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"), +- DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"), +- DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"), +- DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"), +- DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"), +- DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"), +- DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"), +- DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"), +- DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"), +- DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"), +- DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"), +- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), +- DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"), +- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), +- DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"), +- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), +- DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"), +- DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"), +- DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), +- DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"), +- DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), +- DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), +- DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"), +- DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"), +- DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"), +- DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"), +- DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"), +- DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"), +- DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"), +- DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"), +- DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"), +- DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"), +- DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"), +- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"), +- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"), +- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"), +- DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"), +- DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"), +- DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"), ++ DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), ++ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), ++ DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), ++ DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), ++ DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), ++ DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), ++ DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), ++ DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), ++ DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), ++ DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), ++ DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), ++ DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), ++ DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), ++ DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), ++ DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), ++ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), ++ DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), ++ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), ++ DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), ++ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), ++ DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), ++ DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), ++ DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), ++ DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), ++ DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), ++ DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), ++ DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), ++ DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), ++ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), ++ DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), ++ DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), ++ DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), ++ DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), ++ DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), ++ DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), ++ DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), ++ DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), ++ DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), ++ DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), ++ DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), + { .node_name = NULL }, + }; + +diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c +index e23bf04586320..617360e20d86f 100644 +--- a/drivers/clk/ti/clkctrl.c ++++ b/drivers/clk/ti/clkctrl.c +@@ -528,6 +528,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) + char *c; + u16 soc_mask = 0; + ++ if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) && ++ of_node_name_eq(node, "clk")) ++ ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT; ++ + addrp = of_get_address(node, 0, NULL, NULL); + addr = (u32)of_translate_address(node, addrp); + +diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c +index cd62bbb50e8b4..7ce8bb160a592 100644 +--- a/drivers/dma/xilinx/xilinx_dma.c ++++ b/drivers/dma/xilinx/xilinx_dma.c +@@ -3160,9 +3160,10 @@ static int xilinx_dma_probe(struct platform_device *pdev) + + /* Request and map I/O memory */ + xdev->regs = devm_platform_ioremap_resource(pdev, 0); +- if (IS_ERR(xdev->regs)) +- return PTR_ERR(xdev->regs); +- ++ if (IS_ERR(xdev->regs)) { ++ err = PTR_ERR(xdev->regs); ++ goto disable_clks; ++ } + /* Retrieve the DMA engine properties from the device tree */ + xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); + xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; +@@ -3190,7 +3191,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) + if (err < 0) { + dev_err(xdev->dev, + "missing xlnx,num-fstores property\n"); +- return err; ++ goto disable_clks; + } + + err = of_property_read_u32(node, "xlnx,flush-fsync", +@@ -3210,7 +3211,11 @@ static int xilinx_dma_probe(struct platform_device *pdev) + xdev->ext_addr = false; + + /* Set the dma mask bits */ +- dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); ++ err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); ++ if (err < 0) { ++ dev_err(xdev->dev, "DMA mask error %d\n", err); ++ goto disable_clks; ++ } + + /* Initialize the DMA engine */ + xdev->common.dev = &pdev->dev; +@@ -3259,7 +3264,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) + for_each_child_of_node(node, child) { + err = xilinx_dma_child_probe(xdev, child); + if (err < 0) +- goto disable_clks; ++ goto error; + } + + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { +@@ -3294,12 +3299,12 @@ static int xilinx_dma_probe(struct platform_device *pdev) + + return 0; + +-disable_clks: +- xdma_disable_allclks(xdev); + error: + for (i = 0; i < xdev->dma_config->max_channels; i++) + if (xdev->chan[i]) + xilinx_dma_chan_remove(xdev->chan[i]); ++disable_clks: ++ xdma_disable_allclks(xdev); + + return err; + } +diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c +index 3ed7ae0d6781e..96060bf90a24a 100644 +--- a/drivers/firmware/arm_scmi/clock.c ++++ b/drivers/firmware/arm_scmi/clock.c +@@ -450,9 +450,13 @@ static int scmi_clock_count_get(const struct scmi_protocol_handle *ph) + static const struct scmi_clock_info * + scmi_clock_info_get(const struct scmi_protocol_handle *ph, u32 clk_id) + { ++ struct scmi_clock_info *clk; + struct clock_info *ci = ph->get_priv(ph); +- struct scmi_clock_info *clk = ci->clk + clk_id; + ++ if (clk_id >= ci->num_clocks) ++ return NULL; ++ ++ clk = ci->clk + clk_id; + if (!clk->name[0]) + return NULL; + +diff --git a/drivers/firmware/arm_scmi/scmi_pm_domain.c b/drivers/firmware/arm_scmi/scmi_pm_domain.c +index d5dee625de780..0e05a79de82d8 100644 +--- a/drivers/firmware/arm_scmi/scmi_pm_domain.c ++++ b/drivers/firmware/arm_scmi/scmi_pm_domain.c +@@ -112,9 +112,28 @@ static int scmi_pm_domain_probe(struct scmi_device *sdev) + scmi_pd_data->domains = domains; + scmi_pd_data->num_domains = num_domains; + ++ dev_set_drvdata(dev, scmi_pd_data); ++ + return of_genpd_add_provider_onecell(np, scmi_pd_data); + } + ++static void scmi_pm_domain_remove(struct scmi_device *sdev) ++{ ++ int i; ++ struct genpd_onecell_data *scmi_pd_data; ++ struct device *dev = &sdev->dev; ++ struct device_node *np = dev->of_node; ++ ++ of_genpd_del_provider(np); ++ ++ scmi_pd_data = dev_get_drvdata(dev); ++ for (i = 0; i < scmi_pd_data->num_domains; i++) { ++ if (!scmi_pd_data->domains[i]) ++ continue; ++ pm_genpd_remove(scmi_pd_data->domains[i]); ++ } ++} ++ + static const struct scmi_device_id scmi_id_table[] = { + { SCMI_PROTOCOL_POWER, "genpd" }, + { }, +@@ -124,6 +143,7 @@ MODULE_DEVICE_TABLE(scmi, scmi_id_table); + static struct scmi_driver scmi_power_domain_driver = { + .name = "scmi-power-domain", + .probe = scmi_pm_domain_probe, ++ .remove = scmi_pm_domain_remove, + .id_table = scmi_id_table, + }; + module_scmi_driver(scmi_power_domain_driver); +diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c +index 7288c61178380..0b5853fa9d874 100644 +--- a/drivers/firmware/arm_scmi/sensors.c ++++ b/drivers/firmware/arm_scmi/sensors.c +@@ -762,6 +762,10 @@ static int scmi_sensor_config_get(const struct scmi_protocol_handle *ph, + { + int ret; + struct scmi_xfer *t; ++ struct sensors_info *si = ph->get_priv(ph); ++ ++ if (sensor_id >= si->num_sensors) ++ return -EINVAL; + + ret = ph->xops->xfer_get_init(ph, SENSOR_CONFIG_GET, + sizeof(__le32), sizeof(__le32), &t); +@@ -771,7 +775,6 @@ static int scmi_sensor_config_get(const struct scmi_protocol_handle *ph, + put_unaligned_le32(sensor_id, t->tx.buf); + ret = ph->xops->do_xfer(ph, t); + if (!ret) { +- struct sensors_info *si = ph->get_priv(ph); + struct scmi_sensor_info *s = si->sensors + sensor_id; + + *sensor_config = get_unaligned_le64(t->rx.buf); +@@ -788,6 +791,10 @@ static int scmi_sensor_config_set(const struct scmi_protocol_handle *ph, + int ret; + struct scmi_xfer *t; + struct scmi_msg_sensor_config_set *msg; ++ struct sensors_info *si = ph->get_priv(ph); ++ ++ if (sensor_id >= si->num_sensors) ++ return -EINVAL; + + ret = ph->xops->xfer_get_init(ph, SENSOR_CONFIG_SET, + sizeof(*msg), 0, &t); +@@ -800,7 +807,6 @@ static int scmi_sensor_config_set(const struct scmi_protocol_handle *ph, + + ret = ph->xops->do_xfer(ph, t); + if (!ret) { +- struct sensors_info *si = ph->get_priv(ph); + struct scmi_sensor_info *s = si->sensors + sensor_id; + + s->sensor_config = sensor_config; +@@ -831,8 +837,11 @@ static int scmi_sensor_reading_get(const struct scmi_protocol_handle *ph, + int ret; + struct scmi_xfer *t; + struct scmi_msg_sensor_reading_get *sensor; ++ struct scmi_sensor_info *s; + struct sensors_info *si = ph->get_priv(ph); +- struct scmi_sensor_info *s = si->sensors + sensor_id; ++ ++ if (sensor_id >= si->num_sensors) ++ return -EINVAL; + + ret = ph->xops->xfer_get_init(ph, SENSOR_READING_GET, + sizeof(*sensor), 0, &t); +@@ -841,6 +850,7 @@ static int scmi_sensor_reading_get(const struct scmi_protocol_handle *ph, + + sensor = t->tx.buf; + sensor->id = cpu_to_le32(sensor_id); ++ s = si->sensors + sensor_id; + if (s->async) { + sensor->flags = cpu_to_le32(SENSOR_READ_ASYNC); + ret = ph->xops->do_xfer_with_response(ph, t); +@@ -895,9 +905,13 @@ scmi_sensor_reading_get_timestamped(const struct scmi_protocol_handle *ph, + int ret; + struct scmi_xfer *t; + struct scmi_msg_sensor_reading_get *sensor; ++ struct scmi_sensor_info *s; + struct sensors_info *si = ph->get_priv(ph); +- struct scmi_sensor_info *s = si->sensors + sensor_id; + ++ if (sensor_id >= si->num_sensors) ++ return -EINVAL; ++ ++ s = si->sensors + sensor_id; + if (!count || !readings || + (!s->num_axis && count > 1) || (s->num_axis && count > s->num_axis)) + return -EINVAL; +@@ -948,6 +962,9 @@ scmi_sensor_info_get(const struct scmi_protocol_handle *ph, u32 sensor_id) + { + struct sensors_info *si = ph->get_priv(ph); + ++ if (sensor_id >= si->num_sensors) ++ return NULL; ++ + return si->sensors + sensor_id; + } + +diff --git a/drivers/gpio/gpio-ftgpio010.c b/drivers/gpio/gpio-ftgpio010.c +index f422c3e129a0c..f77a965f5780d 100644 +--- a/drivers/gpio/gpio-ftgpio010.c ++++ b/drivers/gpio/gpio-ftgpio010.c +@@ -41,14 +41,12 @@ + * struct ftgpio_gpio - Gemini GPIO state container + * @dev: containing device for this instance + * @gc: gpiochip for this instance +- * @irq: irqchip for this instance + * @base: remapped I/O-memory base + * @clk: silicon clock + */ + struct ftgpio_gpio { + struct device *dev; + struct gpio_chip gc; +- struct irq_chip irq; + void __iomem *base; + struct clk *clk; + }; +@@ -70,6 +68,7 @@ static void ftgpio_gpio_mask_irq(struct irq_data *d) + val = readl(g->base + GPIO_INT_EN); + val &= ~BIT(irqd_to_hwirq(d)); + writel(val, g->base + GPIO_INT_EN); ++ gpiochip_disable_irq(gc, irqd_to_hwirq(d)); + } + + static void ftgpio_gpio_unmask_irq(struct irq_data *d) +@@ -78,6 +77,7 @@ static void ftgpio_gpio_unmask_irq(struct irq_data *d) + struct ftgpio_gpio *g = gpiochip_get_data(gc); + u32 val; + ++ gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + val = readl(g->base + GPIO_INT_EN); + val |= BIT(irqd_to_hwirq(d)); + writel(val, g->base + GPIO_INT_EN); +@@ -221,6 +221,16 @@ static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset, + return 0; + } + ++static const struct irq_chip ftgpio_irq_chip = { ++ .name = "FTGPIO010", ++ .irq_ack = ftgpio_gpio_ack_irq, ++ .irq_mask = ftgpio_gpio_mask_irq, ++ .irq_unmask = ftgpio_gpio_unmask_irq, ++ .irq_set_type = ftgpio_gpio_set_irq_type, ++ .flags = IRQCHIP_IMMUTABLE, ++ GPIOCHIP_IRQ_RESOURCE_HELPERS, ++}; ++ + static int ftgpio_gpio_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -277,14 +287,8 @@ static int ftgpio_gpio_probe(struct platform_device *pdev) + if (!IS_ERR(g->clk)) + g->gc.set_config = ftgpio_gpio_set_config; + +- g->irq.name = "FTGPIO010"; +- g->irq.irq_ack = ftgpio_gpio_ack_irq; +- g->irq.irq_mask = ftgpio_gpio_mask_irq; +- g->irq.irq_unmask = ftgpio_gpio_unmask_irq; +- g->irq.irq_set_type = ftgpio_gpio_set_irq_type; +- + girq = &g->gc.irq; +- girq->chip = &g->irq; ++ gpio_irq_chip_set_chip(girq, &ftgpio_irq_chip); + girq->parent_handler = ftgpio_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), +diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c +index c2523ac26facd..9c8ab1dc60879 100644 +--- a/drivers/gpio/gpiolib-acpi.c ++++ b/drivers/gpio/gpiolib-acpi.c +@@ -32,9 +32,16 @@ MODULE_PARM_DESC(ignore_wake, + "controller@pin combos on which to ignore the ACPI wake flag " + "ignore_wake=controller@pin[,controller@pin[,...]]"); + ++static char *ignore_interrupt; ++module_param(ignore_interrupt, charp, 0444); ++MODULE_PARM_DESC(ignore_interrupt, ++ "controller@pin combos on which to ignore interrupt " ++ "ignore_interrupt=controller@pin[,controller@pin[,...]]"); ++ + struct acpi_gpiolib_dmi_quirk { + bool no_edge_events_on_boot; + char *ignore_wake; ++ char *ignore_interrupt; + }; + + /** +@@ -317,14 +324,15 @@ static struct gpio_desc *acpi_request_own_gpiod(struct gpio_chip *chip, + return desc; + } + +-static bool acpi_gpio_in_ignore_list(const char *controller_in, unsigned int pin_in) ++static bool acpi_gpio_in_ignore_list(const char *ignore_list, const char *controller_in, ++ unsigned int pin_in) + { + const char *controller, *pin_str; + unsigned int pin; + char *endp; + int len; + +- controller = ignore_wake; ++ controller = ignore_list; + while (controller) { + pin_str = strchr(controller, '@'); + if (!pin_str) +@@ -348,7 +356,7 @@ static bool acpi_gpio_in_ignore_list(const char *controller_in, unsigned int pin + + return false; + err: +- pr_err_once("Error: Invalid value for gpiolib_acpi.ignore_wake: %s\n", ignore_wake); ++ pr_err_once("Error: Invalid value for gpiolib_acpi.ignore_...: %s\n", ignore_list); + return false; + } + +@@ -360,7 +368,7 @@ static bool acpi_gpio_irq_is_wake(struct device *parent, + if (agpio->wake_capable != ACPI_WAKE_CAPABLE) + return false; + +- if (acpi_gpio_in_ignore_list(dev_name(parent), pin)) { ++ if (acpi_gpio_in_ignore_list(ignore_wake, dev_name(parent), pin)) { + dev_info(parent, "Ignoring wakeup on pin %u\n", pin); + return false; + } +@@ -427,6 +435,11 @@ static acpi_status acpi_gpiochip_alloc_event(struct acpi_resource *ares, + goto fail_unlock_irq; + } + ++ if (acpi_gpio_in_ignore_list(ignore_interrupt, dev_name(chip->parent), pin)) { ++ dev_info(chip->parent, "Ignoring interrupt on pin %u\n", pin); ++ return AE_OK; ++ } ++ + event = kzalloc(sizeof(*event), GFP_KERNEL); + if (!event) + goto fail_unlock_irq; +@@ -1560,6 +1573,20 @@ static const struct dmi_system_id gpiolib_acpi_quirks[] __initconst = { + .ignore_wake = "INT33FF:01@0", + }, + }, ++ { ++ /* ++ * Interrupt storm caused from edge triggered floating pin ++ * Found in BIOS UX325UAZ.300 ++ * https://bugzilla.kernel.org/show_bug.cgi?id=216208 ++ */ ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), ++ DMI_MATCH(DMI_PRODUCT_NAME, "ZenBook UX325UAZ_UM325UAZ"), ++ }, ++ .driver_data = &(struct acpi_gpiolib_dmi_quirk) { ++ .ignore_interrupt = "AMDI0030:00@18", ++ }, ++ }, + {} /* Terminating entry */ + }; + +@@ -1582,6 +1609,9 @@ static int __init acpi_gpio_setup_params(void) + if (ignore_wake == NULL && quirk && quirk->ignore_wake) + ignore_wake = quirk->ignore_wake; + ++ if (ignore_interrupt == NULL && quirk && quirk->ignore_interrupt) ++ ignore_interrupt = quirk->ignore_interrupt; ++ + return 0; + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +index 69a70a0aaed93..6ab062c63da17 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +@@ -169,6 +169,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev) + for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { + if (adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(6, 0, 0)) + adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc; ++ /* zero sdma_hqd_mask for non-existent engine */ ++ else if (adev->sdma.num_instances == 1) ++ adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc; + else + adev->mes.sdma_hqd_mask[i] = 0xfc; + } +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 0424570c736fa..c781f92db9590 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -5629,7 +5629,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, + plane_info->visible = true; + plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; + +- plane_info->layer_index = 0; ++ plane_info->layer_index = plane_state->normalized_zpos; + + ret = fill_plane_color_attributes(plane_state, plane_info->format, + &plane_info->color_space); +@@ -5697,7 +5697,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, + dc_plane_state->global_alpha = plane_info.global_alpha; + dc_plane_state->global_alpha_value = plane_info.global_alpha_value; + dc_plane_state->dcc = plane_info.dcc; +- dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 ++ dc_plane_state->layer_index = plane_info.layer_index; + dc_plane_state->flip_int_enabled = true; + + /* +@@ -11147,6 +11147,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, + } + } + ++ /* ++ * DC consults the zpos (layer_index in DC terminology) to determine the ++ * hw plane on which to enable the hw cursor (see ++ * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in ++ * atomic state, so call drm helper to normalize zpos. ++ */ ++ drm_atomic_normalize_zpos(dev, state); ++ + /* Remove exiting planes if they are modified */ + for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { + ret = dm_update_plane_state(dc, state, plane, +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +index f4381725b2107..c3d7712e9fd05 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +@@ -46,6 +46,9 @@ + #define TO_CLK_MGR_DCN315(clk_mgr)\ + container_of(clk_mgr, struct clk_mgr_dcn315, base) + ++#define UNSUPPORTED_DCFCLK 10000000 ++#define MIN_DPP_DISP_CLK 100000 ++ + static int dcn315_get_active_display_cnt_wa( + struct dc *dc, + struct dc_state *context) +@@ -146,6 +149,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, + } + } + ++ /* Lock pstate by requesting unsupported dcfclk if change is unsupported */ ++ if (!new_clocks->p_state_change_support) ++ new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK; + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { + clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; + dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); +@@ -159,10 +165,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, + + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { +- if (new_clocks->dppclk_khz < 100000) +- new_clocks->dppclk_khz = 100000; +- if (new_clocks->dispclk_khz < 100000) +- new_clocks->dispclk_khz = 100000; ++ if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK) ++ new_clocks->dppclk_khz = MIN_DPP_DISP_CLK; ++ if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK) ++ new_clocks->dispclk_khz = MIN_DPP_DISP_CLK; + } + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { +@@ -272,7 +278,7 @@ static struct wm_table ddr5_wm_table = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 64.0, ++ .pstate_latency_us = 129.0, + .sr_exit_time_us = 11.5, + .sr_enter_plus_exit_time_us = 14.5, + .valid = true, +@@ -280,7 +286,7 @@ static struct wm_table ddr5_wm_table = { + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 64.0, ++ .pstate_latency_us = 129.0, + .sr_exit_time_us = 11.5, + .sr_enter_plus_exit_time_us = 14.5, + .valid = true, +@@ -288,7 +294,7 @@ static struct wm_table ddr5_wm_table = { + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 64.0, ++ .pstate_latency_us = 129.0, + .sr_exit_time_us = 11.5, + .sr_enter_plus_exit_time_us = 14.5, + .valid = true, +@@ -296,7 +302,7 @@ static struct wm_table ddr5_wm_table = { + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, +- .pstate_latency_us = 64.0, ++ .pstate_latency_us = 129.0, + .sr_exit_time_us = 11.5, + .sr_enter_plus_exit_time_us = 14.5, + .valid = true, +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index a4fc9a6c850ed..b4203a812c4be 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -2857,8 +2857,14 @@ bool perform_link_training_with_retries( + skip_video_pattern); + + /* Transmit idle pattern once training successful. */ +- if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) ++ if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) { + dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); ++ /* Update verified link settings to current one ++ * Because DPIA LT might fallback to lower link setting. ++ */ ++ link->verified_link_cap.link_rate = link->cur_link_settings.link_rate; ++ link->verified_link_cap.lane_count = link->cur_link_settings.lane_count; ++ } + } else { + status = dc_link_dp_perform_link_training(link, + &pipe_ctx->link_res, +@@ -5211,6 +5217,14 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; + ++ /* If this chip cap is set, at least one retimer must exist in the chain ++ * Override count to 1 if we receive a known bad count (0 or an invalid value) */ ++ if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN && ++ (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) { ++ ASSERT(0); ++ link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80; ++ } ++ + /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ + is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 0 && + link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index aee31c785aa9f..4f0ea50eaa839 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -2165,7 +2165,8 @@ static void dce110_setup_audio_dto( + continue; + if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) + continue; +- if (pipe_ctx->stream_res.audio != NULL) { ++ if (pipe_ctx->stream_res.audio != NULL && ++ pipe_ctx->stream_res.audio->enabled == false) { + struct audio_output audio_output; + + build_audio_output(context, pipe_ctx, &audio_output); +@@ -2207,7 +2208,8 @@ static void dce110_setup_audio_dto( + if (!dc_is_dp_signal(pipe_ctx->stream->signal)) + continue; + +- if (pipe_ctx->stream_res.audio != NULL) { ++ if (pipe_ctx->stream_res.audio != NULL && ++ pipe_ctx->stream_res.audio->enabled == false) { + struct audio_output audio_output; + + build_audio_output(context, pipe_ctx, &audio_output); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index ec6aa8d8b251a..213a02a769d45 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1520,6 +1520,7 @@ static void dcn20_update_dchubp_dpp( + /* Any updates are handled in dc interface, just need + * to apply existing for plane enable / opp change */ + if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ++ || pipe_ctx->update_flags.bits.plane_changed + || pipe_ctx->stream->update_flags.bits.gamut_remap + || pipe_ctx->stream->update_flags.bits.out_csc) { + /* dpp/cm gamut remap*/ +diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c +index 9e09db31a937e..5343c82c85944 100644 +--- a/drivers/i2c/busses/i2c-davinci.c ++++ b/drivers/i2c/busses/i2c-davinci.c +@@ -823,7 +823,7 @@ static int davinci_i2c_probe(struct platform_device *pdev) + r = pm_runtime_resume_and_get(dev->dev); + if (r < 0) { + dev_err(dev->dev, "failed to runtime_get device: %d\n", r); +- return r; ++ goto err_pm; + } + + i2c_davinci_init(dev); +@@ -882,6 +882,7 @@ static int davinci_i2c_probe(struct platform_device *pdev) + err_unuse_clocks: + pm_runtime_dont_use_autosuspend(dev->dev); + pm_runtime_put_sync(dev->dev); ++err_pm: + pm_runtime_disable(dev->dev); + + return r; +diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c +index 5e4e2d2182d91..21bfe3448dec8 100644 +--- a/drivers/mmc/core/sd.c ++++ b/drivers/mmc/core/sd.c +@@ -870,7 +870,8 @@ try_again: + * the CCS bit is set as well. We deliberately deviate from the spec in + * regards to this, which allows UHS-I to be supported for SDSC cards. + */ +- if (!mmc_host_is_spi(host) && rocr && (*rocr & 0x01000000)) { ++ if (!mmc_host_is_spi(host) && (ocr & SD_OCR_S18R) && ++ rocr && (*rocr & SD_ROCR_S18A)) { + err = mmc_set_uhs_voltage(host, pocr); + if (err == -EAGAIN) { + retries--; +diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net/ethernet/aquantia/atlantic/aq_main.c +index 88595863d8bc6..8a0af371e7dc7 100644 +--- a/drivers/net/ethernet/aquantia/atlantic/aq_main.c ++++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c +@@ -94,11 +94,8 @@ static int aq_ndev_close(struct net_device *ndev) + int err = 0; + + err = aq_nic_stop(aq_nic); +- if (err < 0) +- goto err_exit; + aq_nic_deinit(aq_nic, true); + +-err_exit: + return err; + } + +diff --git a/drivers/net/ethernet/marvell/prestera/prestera_pci.c b/drivers/net/ethernet/marvell/prestera/prestera_pci.c +index f538a749ebd4d..59470d99f5228 100644 +--- a/drivers/net/ethernet/marvell/prestera/prestera_pci.c ++++ b/drivers/net/ethernet/marvell/prestera/prestera_pci.c +@@ -872,6 +872,7 @@ static void prestera_pci_remove(struct pci_dev *pdev) + static const struct pci_device_id prestera_pci_devices[] = { + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0xC804) }, + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0xC80C) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0xCC1E) }, + { } + }; + MODULE_DEVICE_TABLE(pci, prestera_pci_devices); +diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c +index cfe804bc8d205..148ea636ef979 100644 +--- a/drivers/net/ethernet/mediatek/mtk_ppe.c ++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c +@@ -412,7 +412,7 @@ __mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) + if (entry->hash != 0xffff) { + ppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE; + ppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, +- MTK_FOE_STATE_UNBIND); ++ MTK_FOE_STATE_INVALID); + dma_wmb(); + } + entry->hash = 0xffff; +diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +index c5626ff838058..640e3786c2444 100644 +--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +@@ -1833,8 +1833,8 @@ static void iwl_mvm_parse_ppe(struct iwl_mvm *mvm, + * If nss < MAX: we can set zeros in other streams + */ + if (nss > MAX_HE_SUPP_NSS) { +- IWL_INFO(mvm, "Got NSS = %d - trimming to %d\n", nss, +- MAX_HE_SUPP_NSS); ++ IWL_DEBUG_INFO(mvm, "Got NSS = %d - trimming to %d\n", nss, ++ MAX_HE_SUPP_NSS); + nss = MAX_HE_SUPP_NSS; + } + +diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c +index 07586514991f0..5bc5a0a6a8a72 100644 +--- a/drivers/rpmsg/qcom_glink_native.c ++++ b/drivers/rpmsg/qcom_glink_native.c +@@ -1546,7 +1546,7 @@ static void qcom_glink_rx_close(struct qcom_glink *glink, unsigned int rcid) + cancel_work_sync(&channel->intent_work); + + if (channel->rpdev) { +- strncpy(chinfo.name, channel->name, sizeof(chinfo.name)); ++ strscpy_pad(chinfo.name, channel->name, sizeof(chinfo.name)); + chinfo.src = RPMSG_ADDR_ANY; + chinfo.dst = RPMSG_ADDR_ANY; + +diff --git a/drivers/rpmsg/qcom_smd.c b/drivers/rpmsg/qcom_smd.c +index f7af53891ef92..4ed7c54c85353 100644 +--- a/drivers/rpmsg/qcom_smd.c ++++ b/drivers/rpmsg/qcom_smd.c +@@ -1089,7 +1089,7 @@ static int qcom_smd_create_device(struct qcom_smd_channel *channel) + + /* Assign public information to the rpmsg_device */ + rpdev = &qsdev->rpdev; +- strncpy(rpdev->id.name, channel->name, RPMSG_NAME_SIZE); ++ strscpy_pad(rpdev->id.name, channel->name, RPMSG_NAME_SIZE); + rpdev->src = RPMSG_ADDR_ANY; + rpdev->dst = RPMSG_ADDR_ANY; + +@@ -1323,7 +1323,7 @@ static void qcom_channel_state_worker(struct work_struct *work) + + spin_unlock_irqrestore(&edge->channels_lock, flags); + +- strncpy(chinfo.name, channel->name, sizeof(chinfo.name)); ++ strscpy_pad(chinfo.name, channel->name, sizeof(chinfo.name)); + chinfo.src = RPMSG_ADDR_ANY; + chinfo.dst = RPMSG_ADDR_ANY; + rpmsg_unregister_device(&edge->dev, &chinfo); +diff --git a/drivers/scsi/qedf/qedf_main.c b/drivers/scsi/qedf/qedf_main.c +index 3d6b137314f3f..bbc4d5890ae6a 100644 +--- a/drivers/scsi/qedf/qedf_main.c ++++ b/drivers/scsi/qedf/qedf_main.c +@@ -3686,11 +3686,6 @@ err2: + err1: + scsi_host_put(lport->host); + err0: +- if (qedf) { +- QEDF_INFO(&qedf->dbg_ctx, QEDF_LOG_DISC, "Probe done.\n"); +- +- clear_bit(QEDF_PROBING, &qedf->flags); +- } + return rc; + } + +diff --git a/drivers/usb/mon/mon_bin.c b/drivers/usb/mon/mon_bin.c +index f48a23adbc35d..094e812e9e692 100644 +--- a/drivers/usb/mon/mon_bin.c ++++ b/drivers/usb/mon/mon_bin.c +@@ -1268,6 +1268,11 @@ static int mon_bin_mmap(struct file *filp, struct vm_area_struct *vma) + { + /* don't do anything here: "fault" will set up page table entries */ + vma->vm_ops = &mon_bin_vm_ops; ++ ++ if (vma->vm_flags & VM_WRITE) ++ return -EPERM; ++ ++ vma->vm_flags &= ~VM_MAYWRITE; + vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_private_data = filp->private_data; + mon_bin_vma_open(vma); +diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c +index 52d59be920342..787e63fd7f99b 100644 +--- a/drivers/usb/serial/ftdi_sio.c ++++ b/drivers/usb/serial/ftdi_sio.c +@@ -1319,8 +1319,7 @@ static u32 get_ftdi_divisor(struct tty_struct *tty, + case 38400: div_value = ftdi_sio_b38400; break; + case 57600: div_value = ftdi_sio_b57600; break; + case 115200: div_value = ftdi_sio_b115200; break; +- } /* baud */ +- if (div_value == 0) { ++ default: + dev_dbg(dev, "%s - Baudrate (%d) requested is not supported\n", + __func__, baud); + div_value = ftdi_sio_b9600; +diff --git a/fs/coredump.c b/fs/coredump.c +index ebc43f960b645..f1355e52614a6 100644 +--- a/fs/coredump.c ++++ b/fs/coredump.c +@@ -832,6 +832,38 @@ static int __dump_skip(struct coredump_params *cprm, size_t nr) + } + } + ++static int dump_emit_page(struct coredump_params *cprm, struct page *page) ++{ ++ struct bio_vec bvec = { ++ .bv_page = page, ++ .bv_offset = 0, ++ .bv_len = PAGE_SIZE, ++ }; ++ struct iov_iter iter; ++ struct file *file = cprm->file; ++ loff_t pos = file->f_pos; ++ ssize_t n; ++ ++ if (cprm->to_skip) { ++ if (!__dump_skip(cprm, cprm->to_skip)) ++ return 0; ++ cprm->to_skip = 0; ++ } ++ if (cprm->written + PAGE_SIZE > cprm->limit) ++ return 0; ++ if (dump_interrupted()) ++ return 0; ++ iov_iter_bvec(&iter, WRITE, &bvec, 1, PAGE_SIZE); ++ n = __kernel_write_iter(cprm->file, &iter, &pos); ++ if (n != PAGE_SIZE) ++ return 0; ++ file->f_pos = pos; ++ cprm->written += PAGE_SIZE; ++ cprm->pos += PAGE_SIZE; ++ ++ return 1; ++} ++ + int dump_emit(struct coredump_params *cprm, const void *addr, int nr) + { + if (cprm->to_skip) { +@@ -863,7 +895,6 @@ int dump_user_range(struct coredump_params *cprm, unsigned long start, + + for (addr = start; addr < start + len; addr += PAGE_SIZE) { + struct page *page; +- int stop; + + /* + * To avoid having to allocate page tables for virtual address +@@ -874,10 +905,7 @@ int dump_user_range(struct coredump_params *cprm, unsigned long start, + */ + page = get_dump_page(addr); + if (page) { +- void *kaddr = kmap_local_page(page); +- +- stop = !dump_emit(cprm, kaddr, PAGE_SIZE); +- kunmap_local(kaddr); ++ int stop = !dump_emit_page(cprm, page); + put_page(page); + if (stop) + return 0; +diff --git a/fs/inode.c b/fs/inode.c +index bd4da9c5207ea..08e0857b429e3 100644 +--- a/fs/inode.c ++++ b/fs/inode.c +@@ -192,8 +192,6 @@ int inode_init_always(struct super_block *sb, struct inode *inode) + inode->i_wb_frn_history = 0; + #endif + +- if (security_inode_alloc(inode)) +- goto out; + spin_lock_init(&inode->i_lock); + lockdep_set_class(&inode->i_lock, &sb->s_type->i_lock_key); + +@@ -228,11 +226,12 @@ int inode_init_always(struct super_block *sb, struct inode *inode) + inode->i_fsnotify_mask = 0; + #endif + inode->i_flctx = NULL; ++ ++ if (unlikely(security_inode_alloc(inode))) ++ return -ENOMEM; + this_cpu_inc(nr_inodes); + + return 0; +-out: +- return -ENOMEM; + } + EXPORT_SYMBOL(inode_init_always); + +diff --git a/fs/internal.h b/fs/internal.h +index 87e96b9024ce1..3e206d3e317c4 100644 +--- a/fs/internal.h ++++ b/fs/internal.h +@@ -16,6 +16,7 @@ struct shrink_control; + struct fs_context; + struct user_namespace; + struct pipe_inode_info; ++struct iov_iter; + + /* + * block/bdev.c +@@ -221,3 +222,5 @@ ssize_t do_getxattr(struct user_namespace *mnt_userns, + int setxattr_copy(const char __user *name, struct xattr_ctx *ctx); + int do_setxattr(struct user_namespace *mnt_userns, struct dentry *dentry, + struct xattr_ctx *ctx); ++ ++ssize_t __kernel_write_iter(struct file *file, struct iov_iter *from, loff_t *pos); +diff --git a/fs/read_write.c b/fs/read_write.c +index 397da0236607e..a0a3d35e2c0fd 100644 +--- a/fs/read_write.c ++++ b/fs/read_write.c +@@ -509,14 +509,9 @@ static ssize_t new_sync_write(struct file *filp, const char __user *buf, size_t + } + + /* caller is responsible for file_start_write/file_end_write */ +-ssize_t __kernel_write(struct file *file, const void *buf, size_t count, loff_t *pos) ++ssize_t __kernel_write_iter(struct file *file, struct iov_iter *from, loff_t *pos) + { +- struct kvec iov = { +- .iov_base = (void *)buf, +- .iov_len = min_t(size_t, count, MAX_RW_COUNT), +- }; + struct kiocb kiocb; +- struct iov_iter iter; + ssize_t ret; + + if (WARN_ON_ONCE(!(file->f_mode & FMODE_WRITE))) +@@ -532,8 +527,7 @@ ssize_t __kernel_write(struct file *file, const void *buf, size_t count, loff_t + + init_sync_kiocb(&kiocb, file); + kiocb.ki_pos = pos ? *pos : 0; +- iov_iter_kvec(&iter, WRITE, &iov, 1, iov.iov_len); +- ret = file->f_op->write_iter(&kiocb, &iter); ++ ret = file->f_op->write_iter(&kiocb, from); + if (ret > 0) { + if (pos) + *pos = kiocb.ki_pos; +@@ -543,6 +537,18 @@ ssize_t __kernel_write(struct file *file, const void *buf, size_t count, loff_t + inc_syscw(current); + return ret; + } ++ ++/* caller is responsible for file_start_write/file_end_write */ ++ssize_t __kernel_write(struct file *file, const void *buf, size_t count, loff_t *pos) ++{ ++ struct kvec iov = { ++ .iov_base = (void *)buf, ++ .iov_len = min_t(size_t, count, MAX_RW_COUNT), ++ }; ++ struct iov_iter iter; ++ iov_iter_kvec(&iter, WRITE, &iov, 1, iov.iov_len); ++ return __kernel_write_iter(file, &iter, pos); ++} + /* + * This "EXPORT_SYMBOL_GPL()" is more of a "EXPORT_SYMBOL_DONTUSE()", + * but autofs is one of the few internal kernel users that actually +diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h +index 704111f639937..6dd50ac82d108 100644 +--- a/include/linux/scmi_protocol.h ++++ b/include/linux/scmi_protocol.h +@@ -78,7 +78,7 @@ struct scmi_protocol_handle; + struct scmi_clk_proto_ops { + int (*count_get)(const struct scmi_protocol_handle *ph); + +- const struct scmi_clock_info *(*info_get) ++ const struct scmi_clock_info __must_check *(*info_get) + (const struct scmi_protocol_handle *ph, u32 clk_id); + int (*rate_get)(const struct scmi_protocol_handle *ph, u32 clk_id, + u64 *rate); +@@ -460,7 +460,7 @@ enum scmi_sensor_class { + */ + struct scmi_sensor_proto_ops { + int (*count_get)(const struct scmi_protocol_handle *ph); +- const struct scmi_sensor_info *(*info_get) ++ const struct scmi_sensor_info __must_check *(*info_get) + (const struct scmi_protocol_handle *ph, u32 sensor_id); + int (*trip_point_config)(const struct scmi_protocol_handle *ph, + u32 sensor_id, u8 trip_id, u64 trip_value); +diff --git a/include/net/ieee802154_netdev.h b/include/net/ieee802154_netdev.h +index d0d188c3294bd..a8994f307fc38 100644 +--- a/include/net/ieee802154_netdev.h ++++ b/include/net/ieee802154_netdev.h +@@ -15,6 +15,22 @@ + #ifndef IEEE802154_NETDEVICE_H + #define IEEE802154_NETDEVICE_H + ++#define IEEE802154_REQUIRED_SIZE(struct_type, member) \ ++ (offsetof(typeof(struct_type), member) + \ ++ sizeof(((typeof(struct_type) *)(NULL))->member)) ++ ++#define IEEE802154_ADDR_OFFSET \ ++ offsetof(typeof(struct sockaddr_ieee802154), addr) ++ ++#define IEEE802154_MIN_NAMELEN (IEEE802154_ADDR_OFFSET + \ ++ IEEE802154_REQUIRED_SIZE(struct ieee802154_addr_sa, addr_type)) ++ ++#define IEEE802154_NAMELEN_SHORT (IEEE802154_ADDR_OFFSET + \ ++ IEEE802154_REQUIRED_SIZE(struct ieee802154_addr_sa, short_addr)) ++ ++#define IEEE802154_NAMELEN_LONG (IEEE802154_ADDR_OFFSET + \ ++ IEEE802154_REQUIRED_SIZE(struct ieee802154_addr_sa, hwaddr)) ++ + #include <net/af_ieee802154.h> + #include <linux/netdevice.h> + #include <linux/skbuff.h> +@@ -165,6 +181,27 @@ static inline void ieee802154_devaddr_to_raw(void *raw, __le64 addr) + memcpy(raw, &temp, IEEE802154_ADDR_LEN); + } + ++static inline int ++ieee802154_sockaddr_check_size(struct sockaddr_ieee802154 *daddr, int len) ++{ ++ struct ieee802154_addr_sa *sa; ++ ++ sa = &daddr->addr; ++ if (len < IEEE802154_MIN_NAMELEN) ++ return -EINVAL; ++ switch (sa->addr_type) { ++ case IEEE802154_ADDR_SHORT: ++ if (len < IEEE802154_NAMELEN_SHORT) ++ return -EINVAL; ++ break; ++ case IEEE802154_ADDR_LONG: ++ if (len < IEEE802154_NAMELEN_LONG) ++ return -EINVAL; ++ break; ++ } ++ return 0; ++} ++ + static inline void ieee802154_addr_from_sa(struct ieee802154_addr *a, + const struct ieee802154_addr_sa *sa) + { +diff --git a/include/net/xsk_buff_pool.h b/include/net/xsk_buff_pool.h +index 647722e847b41..f787c3f524b03 100644 +--- a/include/net/xsk_buff_pool.h ++++ b/include/net/xsk_buff_pool.h +@@ -95,7 +95,7 @@ struct xsk_buff_pool *xp_create_and_assign_umem(struct xdp_sock *xs, + struct xdp_umem *umem); + int xp_assign_dev(struct xsk_buff_pool *pool, struct net_device *dev, + u16 queue_id, u16 flags); +-int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem, ++int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_sock *umem_xs, + struct net_device *dev, u16 queue_id); + int xp_alloc_tx_descs(struct xsk_buff_pool *pool, struct xdp_sock *xs); + void xp_destroy(struct xsk_buff_pool *pool); +diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c +index bb1254f076672..9853db0ce487b 100644 +--- a/kernel/bpf/helpers.c ++++ b/kernel/bpf/helpers.c +@@ -1627,26 +1627,12 @@ bpf_base_func_proto(enum bpf_func_id func_id) + return &bpf_ringbuf_discard_proto; + case BPF_FUNC_ringbuf_query: + return &bpf_ringbuf_query_proto; +- case BPF_FUNC_ringbuf_reserve_dynptr: +- return &bpf_ringbuf_reserve_dynptr_proto; +- case BPF_FUNC_ringbuf_submit_dynptr: +- return &bpf_ringbuf_submit_dynptr_proto; +- case BPF_FUNC_ringbuf_discard_dynptr: +- return &bpf_ringbuf_discard_dynptr_proto; + case BPF_FUNC_for_each_map_elem: + return &bpf_for_each_map_elem_proto; + case BPF_FUNC_loop: + return &bpf_loop_proto; + case BPF_FUNC_strncmp: + return &bpf_strncmp_proto; +- case BPF_FUNC_dynptr_from_mem: +- return &bpf_dynptr_from_mem_proto; +- case BPF_FUNC_dynptr_read: +- return &bpf_dynptr_read_proto; +- case BPF_FUNC_dynptr_write: +- return &bpf_dynptr_write_proto; +- case BPF_FUNC_dynptr_data: +- return &bpf_dynptr_data_proto; + default: + break; + } +@@ -1675,6 +1661,20 @@ bpf_base_func_proto(enum bpf_func_id func_id) + return &bpf_timer_cancel_proto; + case BPF_FUNC_kptr_xchg: + return &bpf_kptr_xchg_proto; ++ case BPF_FUNC_ringbuf_reserve_dynptr: ++ return &bpf_ringbuf_reserve_dynptr_proto; ++ case BPF_FUNC_ringbuf_submit_dynptr: ++ return &bpf_ringbuf_submit_dynptr_proto; ++ case BPF_FUNC_ringbuf_discard_dynptr: ++ return &bpf_ringbuf_discard_dynptr_proto; ++ case BPF_FUNC_dynptr_from_mem: ++ return &bpf_dynptr_from_mem_proto; ++ case BPF_FUNC_dynptr_read: ++ return &bpf_dynptr_read_proto; ++ case BPF_FUNC_dynptr_write: ++ return &bpf_dynptr_write_proto; ++ case BPF_FUNC_dynptr_data: ++ return &bpf_dynptr_data_proto; + default: + break; + } +diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c +index dd0fc2a86ce17..d334aeb234076 100644 +--- a/kernel/bpf/syscall.c ++++ b/kernel/bpf/syscall.c +@@ -578,7 +578,7 @@ void bpf_map_free_kptrs(struct bpf_map *map, void *map_value) + if (off_desc->type == BPF_KPTR_UNREF) { + u64 *p = (u64 *)btf_id_ptr; + +- WRITE_ONCE(p, 0); ++ WRITE_ONCE(*p, 0); + continue; + } + old_ptr = xchg(btf_id_ptr, 0); +diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c +index 6a53bcc5cfbb1..48029a390c65a 100644 +--- a/net/bluetooth/hci_core.c ++++ b/net/bluetooth/hci_core.c +@@ -596,6 +596,15 @@ static int hci_dev_do_reset(struct hci_dev *hdev) + + /* Cancel these to avoid queueing non-chained pending work */ + hci_dev_set_flag(hdev, HCI_CMD_DRAIN_WORKQUEUE); ++ /* Wait for ++ * ++ * if (!hci_dev_test_flag(hdev, HCI_CMD_DRAIN_WORKQUEUE)) ++ * queue_delayed_work(&hdev->{cmd,ncmd}_timer) ++ * ++ * inside RCU section to see the flag or complete scheduling. ++ */ ++ synchronize_rcu(); ++ /* Explicitly cancel works in case scheduled after setting the flag. */ + cancel_delayed_work(&hdev->cmd_timer); + cancel_delayed_work(&hdev->ncmd_timer); + +@@ -3871,12 +3880,14 @@ static void hci_cmd_work(struct work_struct *work) + if (res < 0) + __hci_cmd_sync_cancel(hdev, -res); + ++ rcu_read_lock(); + if (test_bit(HCI_RESET, &hdev->flags) || + hci_dev_test_flag(hdev, HCI_CMD_DRAIN_WORKQUEUE)) + cancel_delayed_work(&hdev->cmd_timer); + else +- schedule_delayed_work(&hdev->cmd_timer, +- HCI_CMD_TIMEOUT); ++ queue_delayed_work(hdev->workqueue, &hdev->cmd_timer, ++ HCI_CMD_TIMEOUT); ++ rcu_read_unlock(); + } else { + skb_queue_head(&hdev->cmd_q, skb); + queue_work(hdev->workqueue, &hdev->cmd_work); +diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c +index 2c320a8fe70d7..81e5bcdbbe944 100644 +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -3763,16 +3763,18 @@ static inline void handle_cmd_cnt_and_timer(struct hci_dev *hdev, u8 ncmd) + { + cancel_delayed_work(&hdev->cmd_timer); + ++ rcu_read_lock(); + if (!test_bit(HCI_RESET, &hdev->flags)) { + if (ncmd) { + cancel_delayed_work(&hdev->ncmd_timer); + atomic_set(&hdev->cmd_cnt, 1); + } else { + if (!hci_dev_test_flag(hdev, HCI_CMD_DRAIN_WORKQUEUE)) +- schedule_delayed_work(&hdev->ncmd_timer, +- HCI_NCMD_TIMEOUT); ++ queue_delayed_work(hdev->workqueue, &hdev->ncmd_timer, ++ HCI_NCMD_TIMEOUT); + } + } ++ rcu_read_unlock(); + } + + #define HCI_CC_VL(_op, _func, _min, _max) \ +diff --git a/net/ieee802154/socket.c b/net/ieee802154/socket.c +index 718fb77bb372c..7889e1ef7fad6 100644 +--- a/net/ieee802154/socket.c ++++ b/net/ieee802154/socket.c +@@ -200,8 +200,9 @@ static int raw_bind(struct sock *sk, struct sockaddr *_uaddr, int len) + int err = 0; + struct net_device *dev = NULL; + +- if (len < sizeof(*uaddr)) +- return -EINVAL; ++ err = ieee802154_sockaddr_check_size(uaddr, len); ++ if (err < 0) ++ return err; + + uaddr = (struct sockaddr_ieee802154 *)_uaddr; + if (uaddr->family != AF_IEEE802154) +@@ -493,7 +494,8 @@ static int dgram_bind(struct sock *sk, struct sockaddr *uaddr, int len) + + ro->bound = 0; + +- if (len < sizeof(*addr)) ++ err = ieee802154_sockaddr_check_size(addr, len); ++ if (err < 0) + goto out; + + if (addr->family != AF_IEEE802154) +@@ -564,8 +566,9 @@ static int dgram_connect(struct sock *sk, struct sockaddr *uaddr, + struct dgram_sock *ro = dgram_sk(sk); + int err = 0; + +- if (len < sizeof(*addr)) +- return -EINVAL; ++ err = ieee802154_sockaddr_check_size(addr, len); ++ if (err < 0) ++ return err; + + if (addr->family != AF_IEEE802154) + return -EINVAL; +@@ -604,6 +607,7 @@ static int dgram_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + struct ieee802154_mac_cb *cb; + struct dgram_sock *ro = dgram_sk(sk); + struct ieee802154_addr dst_addr; ++ DECLARE_SOCKADDR(struct sockaddr_ieee802154*, daddr, msg->msg_name); + int hlen, tlen; + int err; + +@@ -612,10 +616,20 @@ static int dgram_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + return -EOPNOTSUPP; + } + +- if (!ro->connected && !msg->msg_name) +- return -EDESTADDRREQ; +- else if (ro->connected && msg->msg_name) +- return -EISCONN; ++ if (msg->msg_name) { ++ if (ro->connected) ++ return -EISCONN; ++ if (msg->msg_namelen < IEEE802154_MIN_NAMELEN) ++ return -EINVAL; ++ err = ieee802154_sockaddr_check_size(daddr, msg->msg_namelen); ++ if (err < 0) ++ return err; ++ ieee802154_addr_from_sa(&dst_addr, &daddr->addr); ++ } else { ++ if (!ro->connected) ++ return -EDESTADDRREQ; ++ dst_addr = ro->dst_addr; ++ } + + if (!ro->bound) + dev = dev_getfirstbyhwtype(sock_net(sk), ARPHRD_IEEE802154); +@@ -651,16 +665,6 @@ static int dgram_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + cb = mac_cb_init(skb); + cb->type = IEEE802154_FC_TYPE_DATA; + cb->ackreq = ro->want_ack; +- +- if (msg->msg_name) { +- DECLARE_SOCKADDR(struct sockaddr_ieee802154*, +- daddr, msg->msg_name); +- +- ieee802154_addr_from_sa(&dst_addr, &daddr->addr); +- } else { +- dst_addr = ro->dst_addr; +- } +- + cb->secen = ro->secen; + cb->secen_override = ro->secen_override; + cb->seclevel = ro->seclevel; +diff --git a/net/xdp/xsk.c b/net/xdp/xsk.c +index 09002387987ea..7e311420aab9f 100644 +--- a/net/xdp/xsk.c ++++ b/net/xdp/xsk.c +@@ -951,8 +951,8 @@ static int xsk_bind(struct socket *sock, struct sockaddr *addr, int addr_len) + goto out_unlock; + } + +- err = xp_assign_dev_shared(xs->pool, umem_xs->umem, +- dev, qid); ++ err = xp_assign_dev_shared(xs->pool, umem_xs, dev, ++ qid); + if (err) { + xp_destroy(xs->pool); + xs->pool = NULL; +diff --git a/net/xdp/xsk_buff_pool.c b/net/xdp/xsk_buff_pool.c +index a71a8c6edf553..ed6c71826d31f 100644 +--- a/net/xdp/xsk_buff_pool.c ++++ b/net/xdp/xsk_buff_pool.c +@@ -212,17 +212,18 @@ err_unreg_pool: + return err; + } + +-int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem, ++int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_sock *umem_xs, + struct net_device *dev, u16 queue_id) + { + u16 flags; ++ struct xdp_umem *umem = umem_xs->umem; + + /* One fill and completion ring required for each queue id. */ + if (!pool->fq || !pool->cq) + return -EINVAL; + + flags = umem->zc ? XDP_ZEROCOPY : XDP_COPY; +- if (pool->uses_need_wakeup) ++ if (umem_xs->pool->uses_need_wakeup) + flags |= XDP_USE_NEED_WAKEUP; + + return xp_assign_dev(pool, dev, queue_id, flags); +diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn +index f5f0d6f09053f..830b9f15fa3f3 100644 +--- a/scripts/Makefile.extrawarn ++++ b/scripts/Makefile.extrawarn +@@ -53,6 +53,7 @@ KBUILD_CFLAGS += -Wno-format-zero-length + KBUILD_CFLAGS += $(call cc-disable-warning, pointer-to-enum-cast) + KBUILD_CFLAGS += -Wno-tautological-constant-out-of-range-compare + KBUILD_CFLAGS += $(call cc-disable-warning, unaligned-access) ++KBUILD_CFLAGS += $(call cc-disable-warning, cast-function-type-strict) + endif + + endif +diff --git a/security/Kconfig.hardening b/security/Kconfig.hardening +index bd2aabb2c60f9..995bc42003e6c 100644 +--- a/security/Kconfig.hardening ++++ b/security/Kconfig.hardening +@@ -22,11 +22,17 @@ menu "Memory initialization" + config CC_HAS_AUTO_VAR_INIT_PATTERN + def_bool $(cc-option,-ftrivial-auto-var-init=pattern) + +-config CC_HAS_AUTO_VAR_INIT_ZERO +- # GCC ignores the -enable flag, so we can test for the feature with +- # a single invocation using the flag, but drop it as appropriate in +- # the Makefile, depending on the presence of Clang. ++config CC_HAS_AUTO_VAR_INIT_ZERO_BARE ++ def_bool $(cc-option,-ftrivial-auto-var-init=zero) ++ ++config CC_HAS_AUTO_VAR_INIT_ZERO_ENABLER ++ # Clang 16 and later warn about using the -enable flag, but it ++ # is required before then. + def_bool $(cc-option,-ftrivial-auto-var-init=zero -enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang) ++ depends on !CC_HAS_AUTO_VAR_INIT_ZERO_BARE ++ ++config CC_HAS_AUTO_VAR_INIT_ZERO ++ def_bool CC_HAS_AUTO_VAR_INIT_ZERO_BARE || CC_HAS_AUTO_VAR_INIT_ZERO_ENABLER + + choice + prompt "Initialize kernel stack variables at function entry" +diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c +index c9d9aa6351ecf..c239d9dbbaefe 100644 +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -1278,6 +1278,7 @@ static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, + set_bit(pcm_idx, &spec->pcm_in_use); + per_pin = get_pin(spec, pin_idx); + per_pin->cvt_nid = per_cvt->cvt_nid; ++ per_pin->silent_stream = false; + hinfo->nid = per_cvt->cvt_nid; + + /* flip stripe flag for the assigned stream if supported */
