commit: be811b7b46514343f3c5d5134e45dffc3a08ea88 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Sat Oct 15 10:05:36 2022 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Sat Oct 15 10:05:36 2022 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=be811b7b
Linux patch 5.10.148 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> 0000_README | 4 + 1147_linux-5.10.148.patch | 2197 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 2201 insertions(+) diff --git a/0000_README b/0000_README index 33d96fa1..cfc507bc 100644 --- a/0000_README +++ b/0000_README @@ -631,6 +631,10 @@ Patch: 1146_linux-5.10.147.patch From: http://www.kernel.org Desc: Linux 5.10.147 +Patch: 1147_linux-5.10.148.patch +From: http://www.kernel.org +Desc: Linux 5.10.148 + Patch: 1500_XATTR_USER_PREFIX.patch From: https://bugs.gentoo.org/show_bug.cgi?id=470644 Desc: Support for namespace user.pax.* on tmpfs. diff --git a/1147_linux-5.10.148.patch b/1147_linux-5.10.148.patch new file mode 100644 index 00000000..3dc73f12 --- /dev/null +++ b/1147_linux-5.10.148.patch @@ -0,0 +1,2197 @@ +diff --git a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt +index 8a9f3559335b5..7e14e26676ec9 100644 +--- a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt ++++ b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt +@@ -34,8 +34,8 @@ Example: + Use specific request line passing from dma + For example, MMC request line is 5 + +- sdhci: sdhci@98e00000 { +- compatible = "moxa,moxart-sdhci"; ++ mmc: mmc@98e00000 { ++ compatible = "moxa,moxart-mmc"; + reg = <0x98e00000 0x5C>; + interrupts = <5 0>; + clocks = <&clk_apb>; +diff --git a/Documentation/process/code-of-conduct-interpretation.rst b/Documentation/process/code-of-conduct-interpretation.rst +index e899f14a4ba24..4f8a06b00f608 100644 +--- a/Documentation/process/code-of-conduct-interpretation.rst ++++ b/Documentation/process/code-of-conduct-interpretation.rst +@@ -51,7 +51,7 @@ the Technical Advisory Board (TAB) or other maintainers if you're + uncertain how to handle situations that come up. It will not be + considered a violation report unless you want it to be. If you are + uncertain about approaching the TAB or any other maintainers, please +-reach out to our conflict mediator, Mishi Choudhary <[email protected]>. ++reach out to our conflict mediator, Joanna Lee <[email protected]>. + + In the end, "be kind to each other" is really what the end goal is for + everybody. We know everyone is human and we all fail at times, but the +diff --git a/Makefile b/Makefile +index 24110f834775a..c40acf09ce29d 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + VERSION = 5 + PATCHLEVEL = 10 +-SUBLEVEL = 147 ++SUBLEVEL = 148 + EXTRAVERSION = + NAME = Dare mighty things + +diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts +index eb5291b0ee3aa..e07b807b4cec5 100644 +--- a/arch/arm/boot/dts/moxart-uc7112lx.dts ++++ b/arch/arm/boot/dts/moxart-uc7112lx.dts +@@ -79,7 +79,7 @@ + clocks = <&ref12>; + }; + +-&sdhci { ++&mmc { + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi +index f5f070a874823..764832ddfa78a 100644 +--- a/arch/arm/boot/dts/moxart.dtsi ++++ b/arch/arm/boot/dts/moxart.dtsi +@@ -93,8 +93,8 @@ + clock-names = "PCLK"; + }; + +- sdhci: sdhci@98e00000 { +- compatible = "moxa,moxart-sdhci"; ++ mmc: mmc@98e00000 { ++ compatible = "moxa,moxart-mmc"; + reg = <0x98e00000 0x5C>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_apb>; +diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c +index 295959487b76d..ae4ba6a6745d4 100644 +--- a/arch/powerpc/mm/book3s64/radix_pgtable.c ++++ b/arch/powerpc/mm/book3s64/radix_pgtable.c +@@ -997,15 +997,6 @@ pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long addre + pmd = *pmdp; + pmd_clear(pmdp); + +- /* +- * pmdp collapse_flush need to ensure that there are no parallel gup +- * walk after this call. This is needed so that we can have stable +- * page ref count when collapsing a page. We don't allow a collapse page +- * if we have gup taken on the page. We can ensure that by sending IPI +- * because gup walk happens with IRQ disabled. +- */ +- serialize_against_pte_lookup(vma->vm_mm); +- + radix__flush_tlb_collapsed_pmd(vma->vm_mm, address); + + return pmd; +diff --git a/arch/um/Makefile b/arch/um/Makefile +index 1cea46ff9bb78..7756151413393 100644 +--- a/arch/um/Makefile ++++ b/arch/um/Makefile +@@ -131,10 +131,18 @@ export LDS_ELF_FORMAT := $(ELF_FORMAT) + # The wrappers will select whether using "malloc" or the kernel allocator. + LINK_WRAPS = -Wl,--wrap,malloc -Wl,--wrap,free -Wl,--wrap,calloc + ++# Avoid binutils 2.39+ warnings by marking the stack non-executable and ++# ignorning warnings for the kallsyms sections. ++LDFLAGS_EXECSTACK = -z noexecstack ++ifeq ($(CONFIG_LD_IS_BFD),y) ++LDFLAGS_EXECSTACK += $(call ld-option,--no-warn-rwx-segments) ++endif ++ + LD_FLAGS_CMDLINE = $(foreach opt,$(KBUILD_LDFLAGS),-Wl,$(opt)) + + # Used by link-vmlinux.sh which has special support for um link + export CFLAGS_vmlinux := $(LINK-y) $(LINK_WRAPS) $(LD_FLAGS_CMDLINE) ++export LDFLAGS_vmlinux := $(LDFLAGS_EXECSTACK) + + # When cleaning we don't include .config, so we don't include + # TT or skas makefiles and don't clean skas_ptregs.h. +diff --git a/arch/x86/um/shared/sysdep/syscalls_32.h b/arch/x86/um/shared/sysdep/syscalls_32.h +index 68fd2cf526fd7..f6e9f84397e79 100644 +--- a/arch/x86/um/shared/sysdep/syscalls_32.h ++++ b/arch/x86/um/shared/sysdep/syscalls_32.h +@@ -6,10 +6,9 @@ + #include <asm/unistd.h> + #include <sysdep/ptrace.h> + +-typedef long syscall_handler_t(struct pt_regs); ++typedef long syscall_handler_t(struct syscall_args); + + extern syscall_handler_t *sys_call_table[]; + + #define EXECUTE_SYSCALL(syscall, regs) \ +- ((long (*)(struct syscall_args)) \ +- (*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs)) ++ ((*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs)) +diff --git a/arch/x86/um/tls_32.c b/arch/x86/um/tls_32.c +index ac8eee093f9cd..66162eafd8e8f 100644 +--- a/arch/x86/um/tls_32.c ++++ b/arch/x86/um/tls_32.c +@@ -65,9 +65,6 @@ static int get_free_idx(struct task_struct* task) + struct thread_struct *t = &task->thread; + int idx; + +- if (!t->arch.tls_array) +- return GDT_ENTRY_TLS_MIN; +- + for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++) + if (!t->arch.tls_array[idx].present) + return idx + GDT_ENTRY_TLS_MIN; +@@ -240,9 +237,6 @@ static int get_tls_entry(struct task_struct *task, struct user_desc *info, + { + struct thread_struct *t = &task->thread; + +- if (!t->arch.tls_array) +- goto clear; +- + if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX) + return -EINVAL; + +diff --git a/arch/x86/um/vdso/Makefile b/arch/x86/um/vdso/Makefile +index 5943387e3f357..5ca366e15c767 100644 +--- a/arch/x86/um/vdso/Makefile ++++ b/arch/x86/um/vdso/Makefile +@@ -62,7 +62,7 @@ quiet_cmd_vdso = VDSO $@ + -Wl,-T,$(filter %.lds,$^) $(filter %.o,$^) && \ + sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@' + +-VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv ++VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv -z noexecstack + GCOV_PROFILE := n + + # +diff --git a/drivers/char/mem.c b/drivers/char/mem.c +index 94c2b556cf972..7d483c3323480 100644 +--- a/drivers/char/mem.c ++++ b/drivers/char/mem.c +@@ -981,8 +981,8 @@ static const struct memdev { + #endif + [5] = { "zero", 0666, &zero_fops, 0 }, + [7] = { "full", 0666, &full_fops, 0 }, +- [8] = { "random", 0666, &random_fops, 0 }, +- [9] = { "urandom", 0666, &urandom_fops, 0 }, ++ [8] = { "random", 0666, &random_fops, FMODE_NOWAIT }, ++ [9] = { "urandom", 0666, &urandom_fops, FMODE_NOWAIT }, + #ifdef CONFIG_PRINTK + [11] = { "kmsg", 0644, &kmsg_fops, 0 }, + #endif +diff --git a/drivers/char/random.c b/drivers/char/random.c +index f769d858eda73..b54481e667307 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -895,20 +895,23 @@ void __cold add_bootloader_randomness(const void *buf, size_t len) + EXPORT_SYMBOL_GPL(add_bootloader_randomness); + + struct fast_pool { +- struct work_struct mix; + unsigned long pool[4]; + unsigned long last; + unsigned int count; ++ struct timer_list mix; + }; + ++static void mix_interrupt_randomness(struct timer_list *work); ++ + static DEFINE_PER_CPU(struct fast_pool, irq_randomness) = { + #ifdef CONFIG_64BIT + #define FASTMIX_PERM SIPHASH_PERMUTATION +- .pool = { SIPHASH_CONST_0, SIPHASH_CONST_1, SIPHASH_CONST_2, SIPHASH_CONST_3 } ++ .pool = { SIPHASH_CONST_0, SIPHASH_CONST_1, SIPHASH_CONST_2, SIPHASH_CONST_3 }, + #else + #define FASTMIX_PERM HSIPHASH_PERMUTATION +- .pool = { HSIPHASH_CONST_0, HSIPHASH_CONST_1, HSIPHASH_CONST_2, HSIPHASH_CONST_3 } ++ .pool = { HSIPHASH_CONST_0, HSIPHASH_CONST_1, HSIPHASH_CONST_2, HSIPHASH_CONST_3 }, + #endif ++ .mix = __TIMER_INITIALIZER(mix_interrupt_randomness, 0) + }; + + /* +@@ -950,7 +953,7 @@ int __cold random_online_cpu(unsigned int cpu) + } + #endif + +-static void mix_interrupt_randomness(struct work_struct *work) ++static void mix_interrupt_randomness(struct timer_list *work) + { + struct fast_pool *fast_pool = container_of(work, struct fast_pool, mix); + /* +@@ -981,7 +984,7 @@ static void mix_interrupt_randomness(struct work_struct *work) + local_irq_enable(); + + mix_pool_bytes(pool, sizeof(pool)); +- credit_init_bits(max(1u, (count & U16_MAX) / 64)); ++ credit_init_bits(clamp_t(unsigned int, (count & U16_MAX) / 64, 1, sizeof(pool) * 8)); + + memzero_explicit(pool, sizeof(pool)); + } +@@ -1004,10 +1007,11 @@ void add_interrupt_randomness(int irq) + if (new_count < 1024 && !time_is_before_jiffies(fast_pool->last + HZ)) + return; + +- if (unlikely(!fast_pool->mix.func)) +- INIT_WORK(&fast_pool->mix, mix_interrupt_randomness); + fast_pool->count |= MIX_INFLIGHT; +- queue_work_on(raw_smp_processor_id(), system_highpri_wq, &fast_pool->mix); ++ if (!timer_pending(&fast_pool->mix)) { ++ fast_pool->mix.expires = jiffies; ++ add_timer_on(&fast_pool->mix, raw_smp_processor_id()); ++ } + } + EXPORT_SYMBOL_GPL(add_interrupt_randomness); + +@@ -1299,6 +1303,11 @@ static ssize_t random_read_iter(struct kiocb *kiocb, struct iov_iter *iter) + { + int ret; + ++ if (!crng_ready() && ++ ((kiocb->ki_flags & (IOCB_NOWAIT | IOCB_NOIO)) || ++ (kiocb->ki_filp->f_flags & O_NONBLOCK))) ++ return -EAGAIN; ++ + ret = wait_for_random_bytes(); + if (ret != 0) + return ret; +diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c +index cbf9922d93d4e..a38c921539793 100644 +--- a/drivers/clk/ti/clk-44xx.c ++++ b/drivers/clk/ti/clk-44xx.c +@@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = { + }; + + static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = { +- "abe-clkctrl:0018:26", ++ "abe_cm:clk:0018:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = { + }; + + static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = { +- "abe-clkctrl:0020:26", ++ "abe_cm:clk:0020:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = { + }; + + static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = { +- "abe-clkctrl:0028:26", ++ "abe_cm:clk:0028:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = + }; + + static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = { +- "abe-clkctrl:0030:26", ++ "abe_cm:clk:0030:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = + }; + + static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = { +- "abe-clkctrl:0038:26", ++ "abe_cm:clk:0038:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = + + static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = { + { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" }, +- { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" }, ++ { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, + { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, +- { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" }, +- { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" }, +- { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" }, +- { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" }, +- { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" }, +- { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" }, +- { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" }, +- { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" }, +- { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" }, +- { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" }, ++ { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, ++ { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" }, ++ { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, ++ { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, ++ { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, ++ { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" }, ++ { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, ++ { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, ++ { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, ++ { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, + { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, + }; +@@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = { + + static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = { + { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" }, +- { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" }, ++ { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" }, + { 0 }, + }; + +@@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = { +- { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" }, ++ { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" }, + { 0 }, + }; + +@@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = { + }; + + static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = { +- { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" }, ++ { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" }, + { 0 }, + }; + +@@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = { + }; + + static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = { +- "l3-init-clkctrl:0038:24", ++ "l3_init_cm:clk:0038:24", + NULL, + }; + + static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = { +- "l3-init-clkctrl:0038:25", ++ "l3_init_cm:clk:0038:25", + NULL, + }; + +@@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon + }; + + static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = { +- "l3-init-clkctrl:0040:24", ++ "l3_init_cm:clk:0040:24", + NULL, + }; + +@@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini + }; + + static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = { +- { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" }, +- { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" }, +- { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" }, ++ { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" }, ++ { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" }, ++ { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" }, + { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" }, + { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" }, + { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" }, + { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" }, +- { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" }, ++ { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" }, + { 0 }, + }; + +@@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = { + }; + + static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = { +- "l4-per-clkctrl:00c0:26", ++ "l4_per_cm:clk:00c0:26", + "pad_clks_ck", + NULL, + }; +@@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = { +- { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" }, +- { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" }, +- { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" }, +- { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" }, +- { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" }, +- { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" }, ++ { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" }, ++ { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" }, ++ { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" }, ++ { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" }, ++ { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" }, ++ { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" }, + { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" }, + { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" }, + { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" }, +@@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons + { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" }, +- { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" }, ++ { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" }, + { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, +- { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" }, ++ { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" }, + { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, +@@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon + { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" }, + { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" }, +- { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" }, ++ { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" }, + { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" }, + { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, +@@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = { + }; + + static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = { +- "emu-sys-clkctrl:0000:22", ++ "emu_sys_cm:clk:0000:22", + NULL, + }; + +@@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init + }; + + static const char * const omap4_stm_clk_div_ck_parents[] __initconst = { +- "emu-sys-clkctrl:0000:20", ++ "emu_sys_cm:clk:0000:20", + NULL, + }; + +@@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = { + * hwmod support. Once hwmod is removed, these can be removed + * also. + */ +- DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"), +- DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"), +- DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"), +- DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"), +- DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"), +- DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"), +- DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"), +- DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"), +- DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"), +- DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"), +- DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"), +- DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"), +- DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"), +- DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"), +- DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"), +- DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"), +- DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"), +- DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"), +- DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"), +- DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"), +- DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"), +- DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"), +- DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"), +- DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"), +- DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"), +- DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"), +- DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"), +- DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"), +- DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"), +- DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"), +- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), +- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), +- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), +- DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"), +- DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"), +- DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"), +- DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"), +- DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"), +- DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"), +- DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"), +- DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"), +- DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"), +- DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"), +- DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"), +- DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"), +- DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"), +- DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"), +- DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"), +- DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"), +- DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"), +- DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"), +- DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"), +- DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"), +- DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"), +- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"), +- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"), +- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"), +- DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"), +- DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"), +- DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"), ++ DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"), ++ DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"), ++ DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"), ++ DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"), ++ DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"), ++ DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"), ++ DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"), ++ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), ++ DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"), ++ DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"), ++ DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"), ++ DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"), ++ DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"), ++ DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"), ++ DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"), ++ DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"), ++ DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"), ++ DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"), ++ DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"), ++ DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"), ++ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"), ++ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"), ++ DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"), ++ DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"), ++ DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"), ++ DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"), ++ DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"), ++ DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"), ++ DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"), ++ DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"), ++ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), ++ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), ++ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), ++ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"), ++ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"), ++ DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"), ++ DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"), ++ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"), ++ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"), ++ DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"), ++ DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"), ++ DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"), ++ DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"), ++ DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"), ++ DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"), ++ DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"), ++ DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"), ++ DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"), ++ DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"), ++ DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"), ++ DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"), ++ DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"), ++ DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"), ++ DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"), ++ DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"), ++ DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"), ++ DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"), + { .node_name = NULL }, + }; + +diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c +index 04a5408085acc..8694bc9f5fc7f 100644 +--- a/drivers/clk/ti/clk-54xx.c ++++ b/drivers/clk/ti/clk-54xx.c +@@ -50,7 +50,7 @@ static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = { + }; + + static const char * const omap5_dmic_gfclk_parents[] __initconst = { +- "abe-clkctrl:0018:26", ++ "abe_cm:clk:0018:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -70,7 +70,7 @@ static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { + }; + + static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { +- "abe-clkctrl:0028:26", ++ "abe_cm:clk:0028:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -83,7 +83,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = + }; + + static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { +- "abe-clkctrl:0030:26", ++ "abe_cm:clk:0030:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -96,7 +96,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = + }; + + static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { +- "abe-clkctrl:0038:26", ++ "abe_cm:clk:0038:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +@@ -136,16 +136,16 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = + + static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { + { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, +- { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" }, ++ { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, + { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, +- { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" }, +- { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" }, +- { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" }, +- { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" }, +- { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" }, +- { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" }, +- { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" }, +- { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" }, ++ { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, ++ { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, ++ { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, ++ { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, ++ { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, ++ { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, ++ { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, ++ { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, + { 0 }, + }; + +@@ -266,12 +266,12 @@ static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { + }; + + static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { +- { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" }, +- { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" }, +- { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" }, +- { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" }, +- { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" }, +- { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" }, ++ { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, ++ { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, ++ { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, ++ { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, ++ { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, ++ { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, + { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, +@@ -343,7 +343,7 @@ static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { +- { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" }, ++ { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, + { 0 }, + }; + +@@ -376,7 +376,7 @@ static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst + }; + + static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = { +- { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" }, ++ { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" }, + { 0 }, + }; + +@@ -387,7 +387,7 @@ static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { + }; + + static const char * const omap5_mmc1_fclk_parents[] __initconst = { +- "l3init-clkctrl:0008:24", ++ "l3init_cm:clk:0008:24", + NULL, + }; + +@@ -403,7 +403,7 @@ static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { + }; + + static const char * const omap5_mmc2_fclk_parents[] __initconst = { +- "l3init-clkctrl:0010:24", ++ "l3init_cm:clk:0010:24", + NULL, + }; + +@@ -428,12 +428,12 @@ static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initcons + }; + + static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { +- "l3init-clkctrl:0038:24", ++ "l3init_cm:clk:0038:24", + NULL, + }; + + static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { +- "l3init-clkctrl:0038:25", ++ "l3init_cm:clk:0038:25", + NULL, + }; + +@@ -492,8 +492,8 @@ static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initcons + }; + + static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { +- { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" }, +- { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, ++ { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, ++ { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, + { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, + { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, +@@ -517,7 +517,7 @@ static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initcon + { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, +- { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" }, ++ { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, + { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, +@@ -547,58 +547,58 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { + static struct ti_dt_clk omap54xx_clks[] = { + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), +- DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"), +- DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"), +- DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"), +- DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"), +- DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"), +- DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"), +- DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"), +- DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"), +- DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"), +- DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"), +- DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"), +- DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"), +- DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"), +- DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"), +- DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"), +- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), +- DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"), +- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), +- DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"), +- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), +- DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"), +- DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"), +- DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), +- DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"), +- DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), +- DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), +- DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"), +- DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"), +- DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"), +- DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"), +- DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"), +- DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"), +- DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"), +- DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"), +- DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"), +- DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"), +- DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"), +- DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"), +- DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"), +- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"), +- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"), +- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"), +- DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"), +- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"), +- DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"), +- DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"), ++ DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), ++ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), ++ DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), ++ DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), ++ DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), ++ DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), ++ DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), ++ DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), ++ DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), ++ DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), ++ DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), ++ DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), ++ DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), ++ DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), ++ DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), ++ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), ++ DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), ++ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), ++ DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), ++ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), ++ DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), ++ DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), ++ DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), ++ DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), ++ DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), ++ DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), ++ DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), ++ DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), ++ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), ++ DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), ++ DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), ++ DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), ++ DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), ++ DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), ++ DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), ++ DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), ++ DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), ++ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), ++ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), ++ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), ++ DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), ++ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), ++ DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), ++ DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), + { .node_name = NULL }, + }; + +diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c +index 08a85c559f795..864c484bde1b4 100644 +--- a/drivers/clk/ti/clkctrl.c ++++ b/drivers/clk/ti/clkctrl.c +@@ -511,6 +511,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) + char *c; + u16 soc_mask = 0; + ++ if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) && ++ of_node_name_eq(node, "clk")) ++ ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT; ++ + addrp = of_get_address(node, 0, NULL, NULL); + addr = (u32)of_translate_address(node, addrp); + +diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c +index cab4719e4cf9c..e76adc31ab66f 100644 +--- a/drivers/dma/xilinx/xilinx_dma.c ++++ b/drivers/dma/xilinx/xilinx_dma.c +@@ -3020,9 +3020,10 @@ static int xilinx_dma_probe(struct platform_device *pdev) + + /* Request and map I/O memory */ + xdev->regs = devm_platform_ioremap_resource(pdev, 0); +- if (IS_ERR(xdev->regs)) +- return PTR_ERR(xdev->regs); +- ++ if (IS_ERR(xdev->regs)) { ++ err = PTR_ERR(xdev->regs); ++ goto disable_clks; ++ } + /* Retrieve the DMA engine properties from the device tree */ + xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); + xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; +@@ -3050,7 +3051,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) + if (err < 0) { + dev_err(xdev->dev, + "missing xlnx,num-fstores property\n"); +- return err; ++ goto disable_clks; + } + + err = of_property_read_u32(node, "xlnx,flush-fsync", +@@ -3070,7 +3071,11 @@ static int xilinx_dma_probe(struct platform_device *pdev) + xdev->ext_addr = false; + + /* Set the dma mask bits */ +- dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); ++ err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); ++ if (err < 0) { ++ dev_err(xdev->dev, "DMA mask error %d\n", err); ++ goto disable_clks; ++ } + + /* Initialize the DMA engine */ + xdev->common.dev = &pdev->dev; +@@ -3115,7 +3120,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) + for_each_child_of_node(node, child) { + err = xilinx_dma_child_probe(xdev, child); + if (err < 0) +- goto disable_clks; ++ goto error; + } + + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { +@@ -3150,12 +3155,12 @@ static int xilinx_dma_probe(struct platform_device *pdev) + + return 0; + +-disable_clks: +- xdma_disable_allclks(xdev); + error: + for (i = 0; i < xdev->dma_config->max_channels; i++) + if (xdev->chan[i]) + xilinx_dma_chan_remove(xdev->chan[i]); ++disable_clks: ++ xdma_disable_allclks(xdev); + + return err; + } +diff --git a/drivers/firmware/arm_scmi/scmi_pm_domain.c b/drivers/firmware/arm_scmi/scmi_pm_domain.c +index a4e4aa9a35426..af74e521f89f3 100644 +--- a/drivers/firmware/arm_scmi/scmi_pm_domain.c ++++ b/drivers/firmware/arm_scmi/scmi_pm_domain.c +@@ -106,9 +106,28 @@ static int scmi_pm_domain_probe(struct scmi_device *sdev) + scmi_pd_data->domains = domains; + scmi_pd_data->num_domains = num_domains; + ++ dev_set_drvdata(dev, scmi_pd_data); ++ + return of_genpd_add_provider_onecell(np, scmi_pd_data); + } + ++static void scmi_pm_domain_remove(struct scmi_device *sdev) ++{ ++ int i; ++ struct genpd_onecell_data *scmi_pd_data; ++ struct device *dev = &sdev->dev; ++ struct device_node *np = dev->of_node; ++ ++ of_genpd_del_provider(np); ++ ++ scmi_pd_data = dev_get_drvdata(dev); ++ for (i = 0; i < scmi_pd_data->num_domains; i++) { ++ if (!scmi_pd_data->domains[i]) ++ continue; ++ pm_genpd_remove(scmi_pd_data->domains[i]); ++ } ++} ++ + static const struct scmi_device_id scmi_id_table[] = { + { SCMI_PROTOCOL_POWER, "genpd" }, + { }, +@@ -118,6 +137,7 @@ MODULE_DEVICE_TABLE(scmi, scmi_id_table); + static struct scmi_driver scmi_power_domain_driver = { + .name = "scmi-power-domain", + .probe = scmi_pm_domain_probe, ++ .remove = scmi_pm_domain_remove, + .id_table = scmi_id_table, + }; + module_scmi_driver(scmi_power_domain_driver); +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 3ac6c7b65a45a..e33fe0207b9e5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -2047,7 +2047,8 @@ static void dce110_setup_audio_dto( + continue; + if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) + continue; +- if (pipe_ctx->stream_res.audio != NULL) { ++ if (pipe_ctx->stream_res.audio != NULL && ++ pipe_ctx->stream_res.audio->enabled == false) { + struct audio_output audio_output; + + build_audio_output(context, pipe_ctx, &audio_output); +@@ -2075,7 +2076,8 @@ static void dce110_setup_audio_dto( + if (!dc_is_dp_signal(pipe_ctx->stream->signal)) + continue; + +- if (pipe_ctx->stream_res.audio != NULL) { ++ if (pipe_ctx->stream_res.audio != NULL && ++ pipe_ctx->stream_res.audio->enabled == false) { + struct audio_output audio_output; + + build_audio_output(context, pipe_ctx, &audio_output); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 3d778760a3b55..8f66eef0c6837 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1481,6 +1481,7 @@ static void dcn20_update_dchubp_dpp( + /* Any updates are handled in dc interface, just need + * to apply existing for plane enable / opp change */ + if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ++ || pipe_ctx->update_flags.bits.plane_changed + || pipe_ctx->stream->update_flags.bits.gamut_remap + || pipe_ctx->stream->update_flags.bits.out_csc) { + #if defined(CONFIG_DRM_AMD_DC_DCN3_0) +diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c +index ba101afcfc27f..70dedc0f7827c 100644 +--- a/drivers/input/joystick/xpad.c ++++ b/drivers/input/joystick/xpad.c +@@ -112,6 +112,8 @@ static const struct xpad_device { + u8 xtype; + } xpad_device[] = { + { 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 }, ++ { 0x03eb, 0xff01, "Wooting One (Legacy)", 0, XTYPE_XBOX360 }, ++ { 0x03eb, 0xff02, "Wooting Two (Legacy)", 0, XTYPE_XBOX360 }, + { 0x044f, 0x0f00, "Thrustmaster Wheel", 0, XTYPE_XBOX }, + { 0x044f, 0x0f03, "Thrustmaster Wheel", 0, XTYPE_XBOX }, + { 0x044f, 0x0f07, "Thrustmaster, Inc. Controller", 0, XTYPE_XBOX }, +@@ -242,6 +244,7 @@ static const struct xpad_device { + { 0x0f0d, 0x0063, "Hori Real Arcade Pro Hayabusa (USA) Xbox One", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE }, + { 0x0f0d, 0x0067, "HORIPAD ONE", 0, XTYPE_XBOXONE }, + { 0x0f0d, 0x0078, "Hori Real Arcade Pro V Kai Xbox One", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE }, ++ { 0x0f0d, 0x00c5, "Hori Fighting Commander ONE", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE }, + { 0x0f30, 0x010b, "Philips Recoil", 0, XTYPE_XBOX }, + { 0x0f30, 0x0202, "Joytech Advanced Controller", 0, XTYPE_XBOX }, + { 0x0f30, 0x8888, "BigBen XBMiniPad Controller", 0, XTYPE_XBOX }, +@@ -258,6 +261,7 @@ static const struct xpad_device { + { 0x1430, 0x8888, "TX6500+ Dance Pad (first generation)", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX }, + { 0x1430, 0xf801, "RedOctane Controller", 0, XTYPE_XBOX360 }, + { 0x146b, 0x0601, "BigBen Interactive XBOX 360 Controller", 0, XTYPE_XBOX360 }, ++ { 0x146b, 0x0604, "Bigben Interactive DAIJA Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, + { 0x1532, 0x0037, "Razer Sabertooth", 0, XTYPE_XBOX360 }, + { 0x1532, 0x0a00, "Razer Atrox Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE }, + { 0x1532, 0x0a03, "Razer Wildcat", 0, XTYPE_XBOXONE }, +@@ -322,6 +326,7 @@ static const struct xpad_device { + { 0x24c6, 0x5502, "Hori Fighting Stick VX Alt", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, + { 0x24c6, 0x5503, "Hori Fighting Edge", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, + { 0x24c6, 0x5506, "Hori SOULCALIBUR V Stick", 0, XTYPE_XBOX360 }, ++ { 0x24c6, 0x5510, "Hori Fighting Commander ONE (Xbox 360/PC Mode)", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, + { 0x24c6, 0x550d, "Hori GEM Xbox controller", 0, XTYPE_XBOX360 }, + { 0x24c6, 0x550e, "Hori Real Arcade Pro V Kai 360", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, + { 0x24c6, 0x551a, "PowerA FUSION Pro Controller", 0, XTYPE_XBOXONE }, +@@ -331,6 +336,14 @@ static const struct xpad_device { + { 0x24c6, 0x5b03, "Thrustmaster Ferrari 458 Racing Wheel", 0, XTYPE_XBOX360 }, + { 0x24c6, 0x5d04, "Razer Sabertooth", 0, XTYPE_XBOX360 }, + { 0x24c6, 0xfafe, "Rock Candy Gamepad for Xbox 360", 0, XTYPE_XBOX360 }, ++ { 0x2563, 0x058d, "OneXPlayer Gamepad", 0, XTYPE_XBOX360 }, ++ { 0x2dc8, 0x2000, "8BitDo Pro 2 Wired Controller fox Xbox", 0, XTYPE_XBOXONE }, ++ { 0x31e3, 0x1100, "Wooting One", 0, XTYPE_XBOX360 }, ++ { 0x31e3, 0x1200, "Wooting Two", 0, XTYPE_XBOX360 }, ++ { 0x31e3, 0x1210, "Wooting Lekker", 0, XTYPE_XBOX360 }, ++ { 0x31e3, 0x1220, "Wooting Two HE", 0, XTYPE_XBOX360 }, ++ { 0x31e3, 0x1300, "Wooting 60HE (AVR)", 0, XTYPE_XBOX360 }, ++ { 0x31e3, 0x1310, "Wooting 60HE (ARM)", 0, XTYPE_XBOX360 }, + { 0x3285, 0x0607, "Nacon GC-100", 0, XTYPE_XBOX360 }, + { 0x3767, 0x0101, "Fanatec Speedster 3 Forceshock Wheel", 0, XTYPE_XBOX }, + { 0xffff, 0xffff, "Chinese-made Xbox Controller", 0, XTYPE_XBOX }, +@@ -416,6 +429,7 @@ static const signed short xpad_abs_triggers[] = { + static const struct usb_device_id xpad_table[] = { + { USB_INTERFACE_INFO('X', 'B', 0) }, /* X-Box USB-IF not approved class */ + XPAD_XBOX360_VENDOR(0x0079), /* GPD Win 2 Controller */ ++ XPAD_XBOX360_VENDOR(0x03eb), /* Wooting Keyboards (Legacy) */ + XPAD_XBOX360_VENDOR(0x044f), /* Thrustmaster X-Box 360 controllers */ + XPAD_XBOX360_VENDOR(0x045e), /* Microsoft X-Box 360 controllers */ + XPAD_XBOXONE_VENDOR(0x045e), /* Microsoft X-Box One controllers */ +@@ -426,6 +440,7 @@ static const struct usb_device_id xpad_table[] = { + { USB_DEVICE(0x0738, 0x4540) }, /* Mad Catz Beat Pad */ + XPAD_XBOXONE_VENDOR(0x0738), /* Mad Catz FightStick TE 2 */ + XPAD_XBOX360_VENDOR(0x07ff), /* Mad Catz GamePad */ ++ XPAD_XBOX360_VENDOR(0x0c12), /* Zeroplus X-Box 360 controllers */ + XPAD_XBOX360_VENDOR(0x0e6f), /* 0x0e6f X-Box 360 controllers */ + XPAD_XBOXONE_VENDOR(0x0e6f), /* 0x0e6f X-Box One controllers */ + XPAD_XBOX360_VENDOR(0x0f0d), /* Hori Controllers */ +@@ -446,8 +461,12 @@ static const struct usb_device_id xpad_table[] = { + XPAD_XBOXONE_VENDOR(0x20d6), /* PowerA Controllers */ + XPAD_XBOX360_VENDOR(0x24c6), /* PowerA Controllers */ + XPAD_XBOXONE_VENDOR(0x24c6), /* PowerA Controllers */ ++ XPAD_XBOX360_VENDOR(0x2563), /* OneXPlayer Gamepad */ ++ XPAD_XBOX360_VENDOR(0x260d), /* Dareu H101 */ ++ XPAD_XBOXONE_VENDOR(0x2dc8), /* 8BitDo Pro 2 Wired Controller for Xbox */ + XPAD_XBOXONE_VENDOR(0x2e24), /* Hyperkin Duke X-Box One pad */ + XPAD_XBOX360_VENDOR(0x2f24), /* GameSir Controllers */ ++ XPAD_XBOX360_VENDOR(0x31e3), /* Wooting Keyboards */ + XPAD_XBOX360_VENDOR(0x3285), /* Nacon GC-100 */ + { } + }; +@@ -1964,7 +1983,6 @@ static struct usb_driver xpad_driver = { + .disconnect = xpad_disconnect, + .suspend = xpad_suspend, + .resume = xpad_resume, +- .reset_resume = xpad_resume, + .id_table = xpad_table, + }; + +diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c +index d3844730eacaf..48eec5fe7397b 100644 +--- a/drivers/misc/pci_endpoint_test.c ++++ b/drivers/misc/pci_endpoint_test.c +@@ -331,6 +331,22 @@ static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, + return false; + } + ++static int pci_endpoint_test_validate_xfer_params(struct device *dev, ++ struct pci_endpoint_test_xfer_param *param, size_t alignment) ++{ ++ if (!param->size) { ++ dev_dbg(dev, "Data size is zero\n"); ++ return -EINVAL; ++ } ++ ++ if (param->size > SIZE_MAX - alignment) { ++ dev_dbg(dev, "Maximum transfer data size exceeded\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, + unsigned long arg) + { +@@ -362,9 +378,11 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, + return false; + } + ++ err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); ++ if (err) ++ return false; ++ + size = param.size; +- if (size > SIZE_MAX - alignment) +- goto err; + + use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); + if (use_dma) +@@ -496,9 +514,11 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, + return false; + } + ++ err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); ++ if (err) ++ return false; ++ + size = param.size; +- if (size > SIZE_MAX - alignment) +- goto err; + + use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); + if (use_dma) +@@ -594,9 +614,11 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, + return false; + } + ++ err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); ++ if (err) ++ return false; ++ + size = param.size; +- if (size > SIZE_MAX - alignment) +- goto err; + + use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); + if (use_dma) +diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c +index 899768ed1688d..868b121ce4f35 100644 +--- a/drivers/mmc/core/sd.c ++++ b/drivers/mmc/core/sd.c +@@ -853,7 +853,8 @@ try_again: + * the CCS bit is set as well. We deliberately deviate from the spec in + * regards to this, which allows UHS-I to be supported for SDSC cards. + */ +- if (!mmc_host_is_spi(host) && rocr && (*rocr & 0x01000000)) { ++ if (!mmc_host_is_spi(host) && (ocr & SD_OCR_S18R) && ++ rocr && (*rocr & SD_ROCR_S18A)) { + err = mmc_set_uhs_voltage(host, pocr); + if (err == -EAGAIN) { + retries--; +diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net/ethernet/aquantia/atlantic/aq_main.c +index 4af0cd9530de6..ff245f75fa3d1 100644 +--- a/drivers/net/ethernet/aquantia/atlantic/aq_main.c ++++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c +@@ -89,11 +89,8 @@ static int aq_ndev_close(struct net_device *ndev) + int err = 0; + + err = aq_nic_stop(aq_nic); +- if (err < 0) +- goto err_exit; + aq_nic_deinit(aq_nic, true); + +-err_exit: + return err; + } + +diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c +index 50190ded7edc7..a6d4ff4760ad1 100644 +--- a/drivers/net/wireless/mac80211_hwsim.c ++++ b/drivers/net/wireless/mac80211_hwsim.c +@@ -3675,6 +3675,8 @@ static int hwsim_cloned_frame_received_nl(struct sk_buff *skb_2, + + rx_status.band = channel->band; + rx_status.rate_idx = nla_get_u32(info->attrs[HWSIM_ATTR_RX_RATE]); ++ if (rx_status.rate_idx >= data2->hw->wiphy->bands[rx_status.band]->n_bitrates) ++ goto out; + rx_status.signal = nla_get_u32(info->attrs[HWSIM_ATTR_SIGNAL]); + + hdr = (void *)skb->data; +diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c +index 4840886532ff7..7cbed0310c09f 100644 +--- a/drivers/rpmsg/qcom_glink_native.c ++++ b/drivers/rpmsg/qcom_glink_native.c +@@ -1472,7 +1472,7 @@ static void qcom_glink_rx_close(struct qcom_glink *glink, unsigned int rcid) + cancel_work_sync(&channel->intent_work); + + if (channel->rpdev) { +- strncpy(chinfo.name, channel->name, sizeof(chinfo.name)); ++ strscpy_pad(chinfo.name, channel->name, sizeof(chinfo.name)); + chinfo.src = RPMSG_ADDR_ANY; + chinfo.dst = RPMSG_ADDR_ANY; + +diff --git a/drivers/rpmsg/qcom_smd.c b/drivers/rpmsg/qcom_smd.c +index 0b1e853d8c91a..b5167ef93abf9 100644 +--- a/drivers/rpmsg/qcom_smd.c ++++ b/drivers/rpmsg/qcom_smd.c +@@ -1073,7 +1073,7 @@ static int qcom_smd_create_device(struct qcom_smd_channel *channel) + + /* Assign public information to the rpmsg_device */ + rpdev = &qsdev->rpdev; +- strncpy(rpdev->id.name, channel->name, RPMSG_NAME_SIZE); ++ strscpy_pad(rpdev->id.name, channel->name, RPMSG_NAME_SIZE); + rpdev->src = RPMSG_ADDR_ANY; + rpdev->dst = RPMSG_ADDR_ANY; + +@@ -1304,7 +1304,7 @@ static void qcom_channel_state_worker(struct work_struct *work) + + spin_unlock_irqrestore(&edge->channels_lock, flags); + +- strncpy(chinfo.name, channel->name, sizeof(chinfo.name)); ++ strscpy_pad(chinfo.name, channel->name, sizeof(chinfo.name)); + chinfo.src = RPMSG_ADDR_ANY; + chinfo.dst = RPMSG_ADDR_ANY; + rpmsg_unregister_device(&edge->dev, &chinfo); +diff --git a/drivers/scsi/qedf/qedf_main.c b/drivers/scsi/qedf/qedf_main.c +index e64457f53da86..de5b6453827c0 100644 +--- a/drivers/scsi/qedf/qedf_main.c ++++ b/drivers/scsi/qedf/qedf_main.c +@@ -3671,11 +3671,6 @@ err2: + err1: + scsi_host_put(lport->host); + err0: +- if (qedf) { +- QEDF_INFO(&qedf->dbg_ctx, QEDF_LOG_DISC, "Probe done.\n"); +- +- clear_bit(QEDF_PROBING, &qedf->flags); +- } + return rc; + } + +diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c +index d4f10c0d813cf..a3bce11ed4b4b 100644 +--- a/drivers/scsi/stex.c ++++ b/drivers/scsi/stex.c +@@ -668,16 +668,17 @@ stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *)) + return 0; + case PASSTHRU_CMD: + if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { +- struct st_drvver ver; ++ const struct st_drvver ver = { ++ .major = ST_VER_MAJOR, ++ .minor = ST_VER_MINOR, ++ .oem = ST_OEM, ++ .build = ST_BUILD_VER, ++ .signature[0] = PASSTHRU_SIGNATURE, ++ .console_id = host->max_id - 1, ++ .host_no = hba->host->host_no, ++ }; + size_t cp_len = sizeof(ver); + +- ver.major = ST_VER_MAJOR; +- ver.minor = ST_VER_MINOR; +- ver.oem = ST_OEM; +- ver.build = ST_BUILD_VER; +- ver.signature[0] = PASSTHRU_SIGNATURE; +- ver.console_id = host->max_id - 1; +- ver.host_no = hba->host->host_no; + cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); + cmd->result = sizeof(ver) == cp_len ? + DID_OK << 16 | COMMAND_COMPLETE << 8 : +diff --git a/drivers/usb/mon/mon_bin.c b/drivers/usb/mon/mon_bin.c +index f48a23adbc35d..094e812e9e692 100644 +--- a/drivers/usb/mon/mon_bin.c ++++ b/drivers/usb/mon/mon_bin.c +@@ -1268,6 +1268,11 @@ static int mon_bin_mmap(struct file *filp, struct vm_area_struct *vma) + { + /* don't do anything here: "fault" will set up page table entries */ + vma->vm_ops = &mon_bin_vm_ops; ++ ++ if (vma->vm_flags & VM_WRITE) ++ return -EPERM; ++ ++ vma->vm_flags &= ~VM_MAYWRITE; + vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_private_data = filp->private_data; + mon_bin_vma_open(vma); +diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c +index 5480bacba39fc..3bfa395c31120 100644 +--- a/drivers/usb/serial/ftdi_sio.c ++++ b/drivers/usb/serial/ftdi_sio.c +@@ -1320,8 +1320,7 @@ static u32 get_ftdi_divisor(struct tty_struct *tty, + case 38400: div_value = ftdi_sio_b38400; break; + case 57600: div_value = ftdi_sio_b57600; break; + case 115200: div_value = ftdi_sio_b115200; break; +- } /* baud */ +- if (div_value == 0) { ++ default: + dev_dbg(dev, "%s - Baudrate (%d) requested is not supported\n", + __func__, baud); + div_value = ftdi_sio_b9600; +diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c +index 586ef5551e76e..b1e844bf31f81 100644 +--- a/drivers/usb/serial/qcserial.c ++++ b/drivers/usb/serial/qcserial.c +@@ -177,6 +177,7 @@ static const struct usb_device_id id_table[] = { + {DEVICE_SWI(0x413c, 0x81b3)}, /* Dell Wireless 5809e Gobi(TM) 4G LTE Mobile Broadband Card (rev3) */ + {DEVICE_SWI(0x413c, 0x81b5)}, /* Dell Wireless 5811e QDL */ + {DEVICE_SWI(0x413c, 0x81b6)}, /* Dell Wireless 5811e QDL */ ++ {DEVICE_SWI(0x413c, 0x81c2)}, /* Dell Wireless 5811e */ + {DEVICE_SWI(0x413c, 0x81cb)}, /* Dell Wireless 5816e QDL */ + {DEVICE_SWI(0x413c, 0x81cc)}, /* Dell Wireless 5816e */ + {DEVICE_SWI(0x413c, 0x81cf)}, /* Dell Wireless 5819 */ +diff --git a/fs/ceph/file.c b/fs/ceph/file.c +index 93d986856f1c9..943655e36a799 100644 +--- a/fs/ceph/file.c ++++ b/fs/ceph/file.c +@@ -703,6 +703,12 @@ int ceph_atomic_open(struct inode *dir, struct dentry *dentry, + if (dentry->d_name.len > NAME_MAX) + return -ENAMETOOLONG; + ++ /* ++ * Do not truncate the file, since atomic_open is called before the ++ * permission check. The caller will do the truncation afterward. ++ */ ++ flags &= ~O_TRUNC; ++ + if (flags & O_CREAT) { + if (ceph_quota_is_max_files_exceeded(dir)) + return -EDQUOT; +@@ -769,9 +775,7 @@ retry: + } + + set_bit(CEPH_MDS_R_PARENT_LOCKED, &req->r_req_flags); +- err = ceph_mdsc_do_request(mdsc, +- (flags & (O_CREAT|O_TRUNC)) ? dir : NULL, +- req); ++ err = ceph_mdsc_do_request(mdsc, (flags & O_CREAT) ? dir : NULL, req); + err = ceph_handle_snapdir(req, dentry, err); + if (err) + goto out_req; +diff --git a/fs/inode.c b/fs/inode.c +index 638d5d5bf42df..9f49e0bdc2f77 100644 +--- a/fs/inode.c ++++ b/fs/inode.c +@@ -168,8 +168,6 @@ int inode_init_always(struct super_block *sb, struct inode *inode) + inode->i_wb_frn_history = 0; + #endif + +- if (security_inode_alloc(inode)) +- goto out; + spin_lock_init(&inode->i_lock); + lockdep_set_class(&inode->i_lock, &sb->s_type->i_lock_key); + +@@ -202,11 +200,12 @@ int inode_init_always(struct super_block *sb, struct inode *inode) + inode->i_fsnotify_mask = 0; + #endif + inode->i_flctx = NULL; ++ ++ if (unlikely(security_inode_alloc(inode))) ++ return -ENOMEM; + this_cpu_inc(nr_inodes); + + return 0; +-out: +- return -ENOMEM; + } + EXPORT_SYMBOL(inode_init_always); + +diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c +index 95684fa3c985a..fb594edc0837c 100644 +--- a/fs/nilfs2/inode.c ++++ b/fs/nilfs2/inode.c +@@ -332,6 +332,7 @@ struct inode *nilfs_new_inode(struct inode *dir, umode_t mode) + struct inode *inode; + struct nilfs_inode_info *ii; + struct nilfs_root *root; ++ struct buffer_head *bh; + int err = -ENOMEM; + ino_t ino; + +@@ -347,11 +348,25 @@ struct inode *nilfs_new_inode(struct inode *dir, umode_t mode) + ii->i_state = BIT(NILFS_I_NEW); + ii->i_root = root; + +- err = nilfs_ifile_create_inode(root->ifile, &ino, &ii->i_bh); ++ err = nilfs_ifile_create_inode(root->ifile, &ino, &bh); + if (unlikely(err)) + goto failed_ifile_create_inode; + /* reference count of i_bh inherits from nilfs_mdt_read_block() */ + ++ if (unlikely(ino < NILFS_USER_INO)) { ++ nilfs_warn(sb, ++ "inode bitmap is inconsistent for reserved inodes"); ++ do { ++ brelse(bh); ++ err = nilfs_ifile_create_inode(root->ifile, &ino, &bh); ++ if (unlikely(err)) ++ goto failed_ifile_create_inode; ++ } while (ino < NILFS_USER_INO); ++ ++ nilfs_info(sb, "repaired inode bitmap for reserved inodes"); ++ } ++ ii->i_bh = bh; ++ + atomic64_inc(&root->inodes_count); + inode_init_owner(inode, dir, mode); + inode->i_ino = ino; +@@ -444,6 +459,8 @@ int nilfs_read_inode_common(struct inode *inode, + inode->i_atime.tv_nsec = le32_to_cpu(raw_inode->i_mtime_nsec); + inode->i_ctime.tv_nsec = le32_to_cpu(raw_inode->i_ctime_nsec); + inode->i_mtime.tv_nsec = le32_to_cpu(raw_inode->i_mtime_nsec); ++ if (nilfs_is_metadata_file_inode(inode) && !S_ISREG(inode->i_mode)) ++ return -EIO; /* this inode is for metadata and corrupted */ + if (inode->i_nlink == 0) + return -ESTALE; /* this inode is deleted */ + +diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c +index 8350c2eaee75a..545f764d70b12 100644 +--- a/fs/nilfs2/segment.c ++++ b/fs/nilfs2/segment.c +@@ -880,9 +880,11 @@ static int nilfs_segctor_create_checkpoint(struct nilfs_sc_info *sci) + nilfs_mdt_mark_dirty(nilfs->ns_cpfile); + nilfs_cpfile_put_checkpoint( + nilfs->ns_cpfile, nilfs->ns_cno, bh_cp); +- } else +- WARN_ON(err == -EINVAL || err == -ENOENT); +- ++ } else if (err == -EINVAL || err == -ENOENT) { ++ nilfs_error(sci->sc_super, ++ "checkpoint creation failed due to metadata corruption."); ++ err = -EIO; ++ } + return err; + } + +@@ -896,7 +898,11 @@ static int nilfs_segctor_fill_in_checkpoint(struct nilfs_sc_info *sci) + err = nilfs_cpfile_get_checkpoint(nilfs->ns_cpfile, nilfs->ns_cno, 0, + &raw_cp, &bh_cp); + if (unlikely(err)) { +- WARN_ON(err == -EINVAL || err == -ENOENT); ++ if (err == -EINVAL || err == -ENOENT) { ++ nilfs_error(sci->sc_super, ++ "checkpoint finalization failed due to metadata corruption."); ++ err = -EIO; ++ } + goto failed_ibh; + } + raw_cp->cp_snapshot_list.ssl_next = 0; +@@ -2791,10 +2797,9 @@ int nilfs_attach_log_writer(struct super_block *sb, struct nilfs_root *root) + inode_attach_wb(nilfs->ns_bdev->bd_inode, NULL); + + err = nilfs_segctor_start_thread(nilfs->ns_writer); +- if (err) { +- kfree(nilfs->ns_writer); +- nilfs->ns_writer = NULL; +- } ++ if (unlikely(err)) ++ nilfs_detach_log_writer(sb); ++ + return err; + } + +diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h +index 4cf524ccab430..ae2de4e1cd6fa 100644 +--- a/include/linux/compiler-gcc.h ++++ b/include/linux/compiler-gcc.h +@@ -54,9 +54,6 @@ + + #define __compiletime_object_size(obj) __builtin_object_size(obj, 0) + +-#define __compiletime_warning(message) __attribute__((__warning__(message))) +-#define __compiletime_error(message) __attribute__((__error__(message))) +- + #if defined(LATENT_ENTROPY_PLUGIN) && !defined(__CHECKER__) + #define __latent_entropy __attribute__((latent_entropy)) + #endif +diff --git a/include/linux/compiler_attributes.h b/include/linux/compiler_attributes.h +index b2a3f4f641a70..08eb06301791d 100644 +--- a/include/linux/compiler_attributes.h ++++ b/include/linux/compiler_attributes.h +@@ -30,6 +30,7 @@ + # define __GCC4_has_attribute___assume_aligned__ (__GNUC_MINOR__ >= 9) + # define __GCC4_has_attribute___copy__ 0 + # define __GCC4_has_attribute___designated_init__ 0 ++# define __GCC4_has_attribute___error__ 1 + # define __GCC4_has_attribute___externally_visible__ 1 + # define __GCC4_has_attribute___no_caller_saved_registers__ 0 + # define __GCC4_has_attribute___noclone__ 1 +@@ -37,6 +38,7 @@ + # define __GCC4_has_attribute___no_sanitize_address__ (__GNUC_MINOR__ >= 8) + # define __GCC4_has_attribute___no_sanitize_undefined__ (__GNUC_MINOR__ >= 9) + # define __GCC4_has_attribute___fallthrough__ 0 ++# define __GCC4_has_attribute___warning__ 1 + #endif + + /* +@@ -136,6 +138,17 @@ + # define __designated_init + #endif + ++/* ++ * Optional: only supported since clang >= 14.0 ++ * ++ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-error-function-attribute ++ */ ++#if __has_attribute(__error__) ++# define __compiletime_error(msg) __attribute__((__error__(msg))) ++#else ++# define __compiletime_error(msg) ++#endif ++ + /* + * Optional: not supported by clang + * +@@ -272,6 +285,17 @@ + */ + #define __used __attribute__((__used__)) + ++/* ++ * Optional: only supported since clang >= 14.0 ++ * ++ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-warning-function-attribute ++ */ ++#if __has_attribute(__warning__) ++# define __compiletime_warning(msg) __attribute__((__warning__(msg))) ++#else ++# define __compiletime_warning(msg) ++#endif ++ + /* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-weak-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-weak-variable-attribute +diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h +index 2a1c202baa1fe..eb2bda017ccb7 100644 +--- a/include/linux/compiler_types.h ++++ b/include/linux/compiler_types.h +@@ -281,12 +281,6 @@ struct ftrace_likely_data { + #ifndef __compiletime_object_size + # define __compiletime_object_size(obj) -1 + #endif +-#ifndef __compiletime_warning +-# define __compiletime_warning(message) +-#endif +-#ifndef __compiletime_error +-# define __compiletime_error(message) +-#endif + + #ifdef __OPTIMIZE__ + # define __compiletime_assert(condition, msg, prefix, suffix) \ +diff --git a/include/net/ieee802154_netdev.h b/include/net/ieee802154_netdev.h +index d0d188c3294bd..a8994f307fc38 100644 +--- a/include/net/ieee802154_netdev.h ++++ b/include/net/ieee802154_netdev.h +@@ -15,6 +15,22 @@ + #ifndef IEEE802154_NETDEVICE_H + #define IEEE802154_NETDEVICE_H + ++#define IEEE802154_REQUIRED_SIZE(struct_type, member) \ ++ (offsetof(typeof(struct_type), member) + \ ++ sizeof(((typeof(struct_type) *)(NULL))->member)) ++ ++#define IEEE802154_ADDR_OFFSET \ ++ offsetof(typeof(struct sockaddr_ieee802154), addr) ++ ++#define IEEE802154_MIN_NAMELEN (IEEE802154_ADDR_OFFSET + \ ++ IEEE802154_REQUIRED_SIZE(struct ieee802154_addr_sa, addr_type)) ++ ++#define IEEE802154_NAMELEN_SHORT (IEEE802154_ADDR_OFFSET + \ ++ IEEE802154_REQUIRED_SIZE(struct ieee802154_addr_sa, short_addr)) ++ ++#define IEEE802154_NAMELEN_LONG (IEEE802154_ADDR_OFFSET + \ ++ IEEE802154_REQUIRED_SIZE(struct ieee802154_addr_sa, hwaddr)) ++ + #include <net/af_ieee802154.h> + #include <linux/netdevice.h> + #include <linux/skbuff.h> +@@ -165,6 +181,27 @@ static inline void ieee802154_devaddr_to_raw(void *raw, __le64 addr) + memcpy(raw, &temp, IEEE802154_ADDR_LEN); + } + ++static inline int ++ieee802154_sockaddr_check_size(struct sockaddr_ieee802154 *daddr, int len) ++{ ++ struct ieee802154_addr_sa *sa; ++ ++ sa = &daddr->addr; ++ if (len < IEEE802154_MIN_NAMELEN) ++ return -EINVAL; ++ switch (sa->addr_type) { ++ case IEEE802154_ADDR_SHORT: ++ if (len < IEEE802154_NAMELEN_SHORT) ++ return -EINVAL; ++ break; ++ case IEEE802154_ADDR_LONG: ++ if (len < IEEE802154_NAMELEN_LONG) ++ return -EINVAL; ++ break; ++ } ++ return 0; ++} ++ + static inline void ieee802154_addr_from_sa(struct ieee802154_addr *a, + const struct ieee802154_addr_sa *sa) + { +diff --git a/include/net/xsk_buff_pool.h b/include/net/xsk_buff_pool.h +index 7a9a23e7a604a..c9a47d3d8f503 100644 +--- a/include/net/xsk_buff_pool.h ++++ b/include/net/xsk_buff_pool.h +@@ -86,7 +86,7 @@ struct xsk_buff_pool *xp_create_and_assign_umem(struct xdp_sock *xs, + struct xdp_umem *umem); + int xp_assign_dev(struct xsk_buff_pool *pool, struct net_device *dev, + u16 queue_id, u16 flags); +-int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem, ++int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_sock *umem_xs, + struct net_device *dev, u16 queue_id); + void xp_destroy(struct xsk_buff_pool *pool); + void xp_release(struct xdp_buff_xsk *xskb); +diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h +index 69ade4fb71aab..4d272e834ca2e 100644 +--- a/include/scsi/scsi_cmnd.h ++++ b/include/scsi/scsi_cmnd.h +@@ -205,7 +205,7 @@ static inline unsigned int scsi_get_resid(struct scsi_cmnd *cmd) + for_each_sg(scsi_sglist(cmd), sg, nseg, __i) + + static inline int scsi_sg_copy_from_buffer(struct scsi_cmnd *cmd, +- void *buf, int buflen) ++ const void *buf, int buflen) + { + return sg_copy_from_buffer(scsi_sglist(cmd), scsi_sg_count(cmd), + buf, buflen); +diff --git a/mm/gup.c b/mm/gup.c +index 6cb7d8ae56f66..b47c751df069a 100644 +--- a/mm/gup.c ++++ b/mm/gup.c +@@ -2128,8 +2128,28 @@ static void __maybe_unused undo_dev_pagemap(int *nr, int nr_start, + } + + #ifdef CONFIG_ARCH_HAS_PTE_SPECIAL +-static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end, +- unsigned int flags, struct page **pages, int *nr) ++/* ++ * Fast-gup relies on pte change detection to avoid concurrent pgtable ++ * operations. ++ * ++ * To pin the page, fast-gup needs to do below in order: ++ * (1) pin the page (by prefetching pte), then (2) check pte not changed. ++ * ++ * For the rest of pgtable operations where pgtable updates can be racy ++ * with fast-gup, we need to do (1) clear pte, then (2) check whether page ++ * is pinned. ++ * ++ * Above will work for all pte-level operations, including THP split. ++ * ++ * For THP collapse, it's a bit more complicated because fast-gup may be ++ * walking a pgtable page that is being freed (pte is still valid but pmd ++ * can be cleared already). To avoid race in such condition, we need to ++ * also check pmd here to make sure pmd doesn't change (corresponds to ++ * pmdp_collapse_flush() in the THP collapse code path). ++ */ ++static int gup_pte_range(pmd_t pmd, pmd_t *pmdp, unsigned long addr, ++ unsigned long end, unsigned int flags, ++ struct page **pages, int *nr) + { + struct dev_pagemap *pgmap = NULL; + int nr_start = *nr, ret = 0; +@@ -2169,7 +2189,8 @@ static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end, + if (!head) + goto pte_unmap; + +- if (unlikely(pte_val(pte) != pte_val(*ptep))) { ++ if (unlikely(pmd_val(pmd) != pmd_val(*pmdp)) || ++ unlikely(pte_val(pte) != pte_val(*ptep))) { + put_compound_head(head, 1, flags); + goto pte_unmap; + } +@@ -2214,8 +2235,9 @@ pte_unmap: + * get_user_pages_fast_only implementation that can pin pages. Thus it's still + * useful to have gup_huge_pmd even if we can't operate on ptes. + */ +-static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end, +- unsigned int flags, struct page **pages, int *nr) ++static int gup_pte_range(pmd_t pmd, pmd_t *pmdp, unsigned long addr, ++ unsigned long end, unsigned int flags, ++ struct page **pages, int *nr) + { + return 0; + } +@@ -2522,7 +2544,7 @@ static int gup_pmd_range(pud_t *pudp, pud_t pud, unsigned long addr, unsigned lo + if (!gup_huge_pd(__hugepd(pmd_val(pmd)), addr, + PMD_SHIFT, next, flags, pages, nr)) + return 0; +- } else if (!gup_pte_range(pmd, addr, next, flags, pages, nr)) ++ } else if (!gup_pte_range(pmd, pmdp, addr, next, flags, pages, nr)) + return 0; + } while (pmdp++, addr = next, addr != end); + +diff --git a/mm/khugepaged.c b/mm/khugepaged.c +index 969e57dde65f9..cf4dceb9682bf 100644 +--- a/mm/khugepaged.c ++++ b/mm/khugepaged.c +@@ -1144,10 +1144,12 @@ static void collapse_huge_page(struct mm_struct *mm, + + pmd_ptl = pmd_lock(mm, pmd); /* probably unnecessary */ + /* +- * After this gup_fast can't run anymore. This also removes +- * any huge TLB entry from the CPU so we won't allow +- * huge and small TLB entries for the same virtual address +- * to avoid the risk of CPU bugs in that area. ++ * This removes any huge TLB entry from the CPU so we won't allow ++ * huge and small TLB entries for the same virtual address to ++ * avoid the risk of CPU bugs in that area. ++ * ++ * Parallel fast GUP is fine since fast GUP will back off when ++ * it detects PMD is changed. + */ + _pmd = pmdp_collapse_flush(vma, address, pmd); + spin_unlock(pmd_ptl); +diff --git a/net/ieee802154/socket.c b/net/ieee802154/socket.c +index c25f7617770c8..7edec210780a3 100644 +--- a/net/ieee802154/socket.c ++++ b/net/ieee802154/socket.c +@@ -201,8 +201,9 @@ static int raw_bind(struct sock *sk, struct sockaddr *_uaddr, int len) + int err = 0; + struct net_device *dev = NULL; + +- if (len < sizeof(*uaddr)) +- return -EINVAL; ++ err = ieee802154_sockaddr_check_size(uaddr, len); ++ if (err < 0) ++ return err; + + uaddr = (struct sockaddr_ieee802154 *)_uaddr; + if (uaddr->family != AF_IEEE802154) +@@ -494,7 +495,8 @@ static int dgram_bind(struct sock *sk, struct sockaddr *uaddr, int len) + + ro->bound = 0; + +- if (len < sizeof(*addr)) ++ err = ieee802154_sockaddr_check_size(addr, len); ++ if (err < 0) + goto out; + + if (addr->family != AF_IEEE802154) +@@ -565,8 +567,9 @@ static int dgram_connect(struct sock *sk, struct sockaddr *uaddr, + struct dgram_sock *ro = dgram_sk(sk); + int err = 0; + +- if (len < sizeof(*addr)) +- return -EINVAL; ++ err = ieee802154_sockaddr_check_size(addr, len); ++ if (err < 0) ++ return err; + + if (addr->family != AF_IEEE802154) + return -EINVAL; +@@ -605,6 +608,7 @@ static int dgram_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + struct ieee802154_mac_cb *cb; + struct dgram_sock *ro = dgram_sk(sk); + struct ieee802154_addr dst_addr; ++ DECLARE_SOCKADDR(struct sockaddr_ieee802154*, daddr, msg->msg_name); + int hlen, tlen; + int err; + +@@ -613,10 +617,20 @@ static int dgram_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + return -EOPNOTSUPP; + } + +- if (!ro->connected && !msg->msg_name) +- return -EDESTADDRREQ; +- else if (ro->connected && msg->msg_name) +- return -EISCONN; ++ if (msg->msg_name) { ++ if (ro->connected) ++ return -EISCONN; ++ if (msg->msg_namelen < IEEE802154_MIN_NAMELEN) ++ return -EINVAL; ++ err = ieee802154_sockaddr_check_size(daddr, msg->msg_namelen); ++ if (err < 0) ++ return err; ++ ieee802154_addr_from_sa(&dst_addr, &daddr->addr); ++ } else { ++ if (!ro->connected) ++ return -EDESTADDRREQ; ++ dst_addr = ro->dst_addr; ++ } + + if (!ro->bound) + dev = dev_getfirstbyhwtype(sock_net(sk), ARPHRD_IEEE802154); +@@ -652,16 +666,6 @@ static int dgram_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + cb = mac_cb_init(skb); + cb->type = IEEE802154_FC_TYPE_DATA; + cb->ackreq = ro->want_ack; +- +- if (msg->msg_name) { +- DECLARE_SOCKADDR(struct sockaddr_ieee802154*, +- daddr, msg->msg_name); +- +- ieee802154_addr_from_sa(&dst_addr, &daddr->addr); +- } else { +- dst_addr = ro->dst_addr; +- } +- + cb->secen = ro->secen; + cb->secen_override = ro->secen_override; + cb->seclevel = ro->seclevel; +diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c +index e991abb45f68f..97a63b940482d 100644 +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -1975,10 +1975,11 @@ ieee80211_rx_h_decrypt(struct ieee80211_rx_data *rx) + + if (mmie_keyidx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS || + mmie_keyidx >= NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS + +- NUM_DEFAULT_BEACON_KEYS) { +- cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, +- skb->data, +- skb->len); ++ NUM_DEFAULT_BEACON_KEYS) { ++ if (rx->sdata->dev) ++ cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, ++ skb->data, ++ skb->len); + return RX_DROP_MONITOR; /* unexpected BIP keyidx */ + } + +@@ -2126,7 +2127,8 @@ ieee80211_rx_h_decrypt(struct ieee80211_rx_data *rx) + /* either the frame has been decrypted or will be dropped */ + status->flag |= RX_FLAG_DECRYPTED; + +- if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE)) ++ if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE && ++ rx->sdata->dev)) + cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, + skb->data, skb->len); + +diff --git a/net/mac80211/util.c b/net/mac80211/util.c +index a1f129292ad88..11d5686893c6a 100644 +--- a/net/mac80211/util.c ++++ b/net/mac80211/util.c +@@ -1409,6 +1409,8 @@ static size_t ieee802_11_find_bssid_profile(const u8 *start, size_t len, + for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, start, len) { + if (elem->datalen < 2) + continue; ++ if (elem->data[0] < 1 || elem->data[0] > 8) ++ continue; + + for_each_element(sub, elem->data + 1, elem->datalen - 1) { + u8 new_bssid[ETH_ALEN]; +diff --git a/net/wireless/scan.c b/net/wireless/scan.c +index 6dc9b7e22b71d..22d169923261f 100644 +--- a/net/wireless/scan.c ++++ b/net/wireless/scan.c +@@ -143,18 +143,12 @@ static inline void bss_ref_get(struct cfg80211_registered_device *rdev, + lockdep_assert_held(&rdev->bss_lock); + + bss->refcount++; +- if (bss->pub.hidden_beacon_bss) { +- bss = container_of(bss->pub.hidden_beacon_bss, +- struct cfg80211_internal_bss, +- pub); +- bss->refcount++; +- } +- if (bss->pub.transmitted_bss) { +- bss = container_of(bss->pub.transmitted_bss, +- struct cfg80211_internal_bss, +- pub); +- bss->refcount++; +- } ++ ++ if (bss->pub.hidden_beacon_bss) ++ bss_from_pub(bss->pub.hidden_beacon_bss)->refcount++; ++ ++ if (bss->pub.transmitted_bss) ++ bss_from_pub(bss->pub.transmitted_bss)->refcount++; + } + + static inline void bss_ref_put(struct cfg80211_registered_device *rdev, +@@ -304,7 +298,8 @@ static size_t cfg80211_gen_new_ie(const u8 *ie, size_t ielen, + tmp_old = cfg80211_find_ie(WLAN_EID_SSID, ie, ielen); + tmp_old = (tmp_old) ? tmp_old + tmp_old[1] + 2 : ie; + +- while (tmp_old + tmp_old[1] + 2 - ie <= ielen) { ++ while (tmp_old + 2 - ie <= ielen && ++ tmp_old + tmp_old[1] + 2 - ie <= ielen) { + if (tmp_old[0] == 0) { + tmp_old++; + continue; +@@ -364,7 +359,8 @@ static size_t cfg80211_gen_new_ie(const u8 *ie, size_t ielen, + * copied to new ie, skip ssid, capability, bssid-index ie + */ + tmp_new = sub_copy; +- while (tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { ++ while (tmp_new + 2 - sub_copy <= subie_len && ++ tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { + if (!(tmp_new[0] == WLAN_EID_NON_TX_BSSID_CAP || + tmp_new[0] == WLAN_EID_SSID)) { + memcpy(pos, tmp_new, tmp_new[1] + 2); +@@ -429,6 +425,15 @@ cfg80211_add_nontrans_list(struct cfg80211_bss *trans_bss, + + rcu_read_unlock(); + ++ /* ++ * This is a bit weird - it's not on the list, but already on another ++ * one! The only way that could happen is if there's some BSSID/SSID ++ * shared by multiple APs in their multi-BSSID profiles, potentially ++ * with hidden SSID mixed in ... ignore it. ++ */ ++ if (!list_empty(&nontrans_bss->nontrans_list)) ++ return -EINVAL; ++ + /* add to the list */ + list_add_tail(&nontrans_bss->nontrans_list, &trans_bss->nontrans_list); + return 0; +@@ -1597,6 +1602,23 @@ struct cfg80211_non_tx_bss { + u8 bssid_index; + }; + ++static void cfg80211_update_hidden_bsses(struct cfg80211_internal_bss *known, ++ const struct cfg80211_bss_ies *new_ies, ++ const struct cfg80211_bss_ies *old_ies) ++{ ++ struct cfg80211_internal_bss *bss; ++ ++ /* Assign beacon IEs to all sub entries */ ++ list_for_each_entry(bss, &known->hidden_list, hidden_list) { ++ const struct cfg80211_bss_ies *ies; ++ ++ ies = rcu_access_pointer(bss->pub.beacon_ies); ++ WARN_ON(ies != old_ies); ++ ++ rcu_assign_pointer(bss->pub.beacon_ies, new_ies); ++ } ++} ++ + static bool + cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, + struct cfg80211_internal_bss *known, +@@ -1620,7 +1642,6 @@ cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, + kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); + } else if (rcu_access_pointer(new->pub.beacon_ies)) { + const struct cfg80211_bss_ies *old; +- struct cfg80211_internal_bss *bss; + + if (known->pub.hidden_beacon_bss && + !list_empty(&known->hidden_list)) { +@@ -1648,16 +1669,7 @@ cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, + if (old == rcu_access_pointer(known->pub.ies)) + rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies); + +- /* Assign beacon IEs to all sub entries */ +- list_for_each_entry(bss, &known->hidden_list, hidden_list) { +- const struct cfg80211_bss_ies *ies; +- +- ies = rcu_access_pointer(bss->pub.beacon_ies); +- WARN_ON(ies != old); +- +- rcu_assign_pointer(bss->pub.beacon_ies, +- new->pub.beacon_ies); +- } ++ cfg80211_update_hidden_bsses(known, new->pub.beacon_ies, old); + + if (old) + kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); +@@ -1734,6 +1746,8 @@ cfg80211_bss_update(struct cfg80211_registered_device *rdev, + new->refcount = 1; + INIT_LIST_HEAD(&new->hidden_list); + INIT_LIST_HEAD(&new->pub.nontrans_list); ++ /* we'll set this later if it was non-NULL */ ++ new->pub.transmitted_bss = NULL; + + if (rcu_access_pointer(tmp->pub.proberesp_ies)) { + hidden = rb_find_bss(rdev, tmp, BSS_CMP_HIDE_ZLEN); +@@ -1971,10 +1985,15 @@ cfg80211_inform_single_bss_data(struct wiphy *wiphy, + spin_lock_bh(&rdev->bss_lock); + if (cfg80211_add_nontrans_list(non_tx_data->tx_bss, + &res->pub)) { +- if (__cfg80211_unlink_bss(rdev, res)) ++ if (__cfg80211_unlink_bss(rdev, res)) { + rdev->bss_generation++; ++ res = NULL; ++ } + } + spin_unlock_bh(&rdev->bss_lock); ++ ++ if (!res) ++ return NULL; + } + + trace_cfg80211_return_bss(&res->pub); +@@ -2093,6 +2112,8 @@ static void cfg80211_parse_mbssid_data(struct wiphy *wiphy, + for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, ie, ielen) { + if (elem->datalen < 4) + continue; ++ if (elem->data[0] < 1 || (int)elem->data[0] > 8) ++ continue; + for_each_element(sub, elem->data + 1, elem->datalen - 1) { + u8 profile_len; + +@@ -2228,7 +2249,7 @@ cfg80211_update_notlisted_nontrans(struct wiphy *wiphy, + size_t new_ie_len; + struct cfg80211_bss_ies *new_ies; + const struct cfg80211_bss_ies *old; +- u8 cpy_len; ++ size_t cpy_len; + + lockdep_assert_held(&wiphy_to_rdev(wiphy)->bss_lock); + +@@ -2295,6 +2316,8 @@ cfg80211_update_notlisted_nontrans(struct wiphy *wiphy, + } else { + old = rcu_access_pointer(nontrans_bss->beacon_ies); + rcu_assign_pointer(nontrans_bss->beacon_ies, new_ies); ++ cfg80211_update_hidden_bsses(bss_from_pub(nontrans_bss), ++ new_ies, old); + rcu_assign_pointer(nontrans_bss->ies, new_ies); + if (old) + kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); +diff --git a/net/xdp/xsk.c b/net/xdp/xsk.c +index ca4716b92774b..691841dc6d334 100644 +--- a/net/xdp/xsk.c ++++ b/net/xdp/xsk.c +@@ -742,8 +742,8 @@ static int xsk_bind(struct socket *sock, struct sockaddr *addr, int addr_len) + goto out_unlock; + } + +- err = xp_assign_dev_shared(xs->pool, umem_xs->umem, +- dev, qid); ++ err = xp_assign_dev_shared(xs->pool, umem_xs, dev, ++ qid); + if (err) { + xp_destroy(xs->pool); + xs->pool = NULL; +diff --git a/net/xdp/xsk_buff_pool.c b/net/xdp/xsk_buff_pool.c +index e63a285a98565..c347e52f58df8 100644 +--- a/net/xdp/xsk_buff_pool.c ++++ b/net/xdp/xsk_buff_pool.c +@@ -198,17 +198,18 @@ int xp_assign_dev(struct xsk_buff_pool *pool, struct net_device *dev, + return __xp_assign_dev(pool, dev, queue_id, flags); + } + +-int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem, ++int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_sock *umem_xs, + struct net_device *dev, u16 queue_id) + { + u16 flags; ++ struct xdp_umem *umem = umem_xs->umem; + + /* One fill and completion ring required for each queue id. */ + if (!pool->fq || !pool->cq) + return -EINVAL; + + flags = umem->zc ? XDP_ZEROCOPY : XDP_COPY; +- if (pool->uses_need_wakeup) ++ if (umem_xs->pool->uses_need_wakeup) + flags |= XDP_USE_NEED_WAKEUP; + + return __xp_assign_dev(pool, dev, queue_id, flags); +diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn +index 23d3967786b9f..fe327a4532ddb 100644 +--- a/scripts/Makefile.extrawarn ++++ b/scripts/Makefile.extrawarn +@@ -52,6 +52,7 @@ KBUILD_CFLAGS += -Wno-format-zero-length + KBUILD_CFLAGS += $(call cc-disable-warning, pointer-to-enum-cast) + KBUILD_CFLAGS += -Wno-tautological-constant-out-of-range-compare + KBUILD_CFLAGS += $(call cc-disable-warning, unaligned-access) ++KBUILD_CFLAGS += $(call cc-disable-warning, cast-function-type-strict) + endif + + endif +diff --git a/security/integrity/platform_certs/load_uefi.c b/security/integrity/platform_certs/load_uefi.c +index 555d2dfc0ff79..185c609c6e380 100644 +--- a/security/integrity/platform_certs/load_uefi.c ++++ b/security/integrity/platform_certs/load_uefi.c +@@ -30,7 +30,7 @@ static const struct dmi_system_id uefi_skip_cert[] = { + { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "MacBookAir8,1") }, + { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "MacBookAir8,2") }, + { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "MacBookAir9,1") }, +- { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "MacMini8,1") }, ++ { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "Macmini8,1") }, + { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "MacPro7,1") }, + { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "iMac20,1") }, + { UEFI_QUIRK_SKIP_CERT("Apple Inc.", "iMac20,2") }, +diff --git a/sound/core/oss/pcm_oss.c b/sound/core/oss/pcm_oss.c +index f88de74da1eb3..de6f94bee50b9 100644 +--- a/sound/core/oss/pcm_oss.c ++++ b/sound/core/oss/pcm_oss.c +@@ -1662,13 +1662,14 @@ static int snd_pcm_oss_sync(struct snd_pcm_oss_file *pcm_oss_file) + runtime = substream->runtime; + if (atomic_read(&substream->mmap_count)) + goto __direct; +- if ((err = snd_pcm_oss_make_ready(substream)) < 0) +- return err; + atomic_inc(&runtime->oss.rw_ref); + if (mutex_lock_interruptible(&runtime->oss.params_lock)) { + atomic_dec(&runtime->oss.rw_ref); + return -ERESTARTSYS; + } ++ err = snd_pcm_oss_make_ready_locked(substream); ++ if (err < 0) ++ goto unlock; + format = snd_pcm_oss_format_from(runtime->oss.format); + width = snd_pcm_format_physical_width(format); + if (runtime->oss.buffer_used > 0) { +diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c +index 79b8d4258fd3b..26dfa8558792f 100644 +--- a/sound/pci/hda/hda_intel.c ++++ b/sound/pci/hda/hda_intel.c +@@ -2588,7 +2588,8 @@ static const struct pci_device_id azx_ids[] = { + .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, + /* Poulsbo */ + { PCI_DEVICE(0x8086, 0x811b), +- .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, ++ .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | ++ AZX_DCAPS_POSFIX_LPIB }, + /* Oaktrail */ + { PCI_DEVICE(0x8086, 0x080a), + .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, +diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c +index e6f261e8c5ae7..c3fcf478037f9 100644 +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -1269,6 +1269,7 @@ static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, + set_bit(pcm_idx, &spec->pcm_in_use); + per_pin = get_pin(spec, pin_idx); + per_pin->cvt_nid = per_cvt->cvt_nid; ++ per_pin->silent_stream = false; + hinfo->nid = per_cvt->cvt_nid; + + /* flip stripe flag for the assigned stream if supported */ +diff --git a/tools/perf/util/get_current_dir_name.c b/tools/perf/util/get_current_dir_name.c +index b205d929245f5..e68935e9ac8ce 100644 +--- a/tools/perf/util/get_current_dir_name.c ++++ b/tools/perf/util/get_current_dir_name.c +@@ -3,8 +3,9 @@ + // + #ifndef HAVE_GET_CURRENT_DIR_NAME + #include "get_current_dir_name.h" ++#include <limits.h> ++#include <string.h> + #include <unistd.h> +-#include <stdlib.h> + + /* Android's 'bionic' library, for one, doesn't have this */ +
