commit: e52a88b468775df39735b75167f2ae78cf268b8b Author: Yuan Liao <liaoyuan <AT> gmail <DOT> com> AuthorDate: Thu Dec 22 00:33:21 2022 +0000 Commit: Yuan Liao <liaoyuan <AT> gmail <DOT> com> CommitDate: Thu Dec 22 00:40:21 2022 +0000 URL: https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=e52a88b4
games-emulation/dosbox-x: Backport upstream LTO ODR fix to 2022.08.0 Not bumping revision for this change because the ebuild for 2022.08.0 has just been revision-bumped in the previous commit. Bug: https://bugs.gentoo.org/859973 Signed-off-by: Yuan Liao <liaoyuan <AT> gmail.com> .../dosbox-x/dosbox-x-2022.08.0-r1.ebuild | 14 +- .../files/dosbox-x-2022.08.0-fix-lto-odr.patch | 368 +++++++++++++++++++++ 2 files changed, 376 insertions(+), 6 deletions(-) diff --git a/games-emulation/dosbox-x/dosbox-x-2022.08.0-r1.ebuild b/games-emulation/dosbox-x/dosbox-x-2022.08.0-r1.ebuild index bec3c9a2e..d208c6afb 100644 --- a/games-emulation/dosbox-x/dosbox-x-2022.08.0-r1.ebuild +++ b/games-emulation/dosbox-x/dosbox-x-2022.08.0-r1.ebuild @@ -5,7 +5,7 @@ EAPI=8 -inherit autotools flag-o-matic toolchain-funcs xdg +inherit autotools toolchain-funcs xdg if [[ "${PV}" == 9999 ]]; then inherit git-r3 @@ -68,6 +68,13 @@ DEPEND=" ${RDEPEND} " +PATCHES=( + # https://bugs.gentoo.org/859973 + # https://github.com/joncampbell123/dosbox-x/issues/3663 + # https://github.com/joncampbell123/dosbox-x/pull/3710 + "${FILESDIR}/${P}-fix-lto-odr.patch" +) + pkg_pretend() { if use ffmpeg && use !png; then ewarn "Setting the 'ffmpeg' USE flag when the 'png' USE flag is" @@ -111,11 +118,6 @@ src_prepare() { die "Failed to remove check for setcap in Makefile.am" eautoreconf - - # https://bugs.gentoo.org/859973 - # https://github.com/joncampbell123/dosbox-x/issues/3663 - # No upstream response regarding LTO yet; disable it for now - filter-lto } src_configure() { diff --git a/games-emulation/dosbox-x/files/dosbox-x-2022.08.0-fix-lto-odr.patch b/games-emulation/dosbox-x/files/dosbox-x-2022.08.0-fix-lto-odr.patch new file mode 100644 index 000000000..daf0ae2f2 --- /dev/null +++ b/games-emulation/dosbox-x/files/dosbox-x-2022.08.0-fix-lto-odr.patch @@ -0,0 +1,368 @@ +From 7573870bb856ade326033824d7a2ba6fb4fcdfaf Mon Sep 17 00:00:00 2001 +From: Jookia <[email protected]> +Date: Wed, 7 Sep 2022 10:44:48 +1000 +Subject: [PATCH 1/2] libs: Namespace PhysFS lzmasdk + +--- + src/libs/physfs/physfs_archiver_7z.c | 1 + + src/libs/physfs/physfs_lzmasdk.h | 6 +++++- + 2 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/src/libs/physfs/physfs_archiver_7z.c b/src/libs/physfs/physfs_archiver_7z.c +index 604fd13981a..4095f031710 100644 +--- a/src/libs/physfs/physfs_archiver_7z.c ++++ b/src/libs/physfs/physfs_archiver_7z.c +@@ -12,6 +12,7 @@ + #if PHYSFS_SUPPORTS_7Z + + #include "physfs_lzmasdk.h" ++using namespace physfs_lzmasdk; + + typedef struct + { +diff --git a/src/libs/physfs/physfs_lzmasdk.h b/src/libs/physfs/physfs_lzmasdk.h +index 239f8f0d1a2..f0abaa136a8 100644 +--- a/src/libs/physfs/physfs_lzmasdk.h ++++ b/src/libs/physfs/physfs_lzmasdk.h +@@ -7,13 +7,15 @@ Igor Pavlov. http://www.7-zip.org/sdk.html + --ryan. */ + + +- + /* 7zTypes.h -- Basic types + 2013-11-12 : Igor Pavlov : Public domain */ + + #ifndef __7Z_TYPES_H + #define __7Z_TYPES_H + ++// Jookia: Added to avoid conflict with other LZMA libraries ++namespace physfs_lzmasdk { ++ + #ifdef _WIN32 + /* #include <windows.h> */ + #endif +@@ -6030,6 +6032,8 @@ static SRes Lzma2Dec_DecodeToDic(CLzma2Dec *p, SizeT dicLimit, + return SZ_OK; + } + ++} ++ + #endif /* _INCLUDE_PHYSFS_LZMASDK_H_ */ + + /* end of physfs_lzmasdk.h ... */ + +From 7fb29da0ec0aff0c35c3dce2e8da14205103d5b5 Mon Sep 17 00:00:00 2001 +From: Jookia <[email protected]> +Date: Wed, 7 Sep 2022 10:56:40 +1000 +Subject: [PATCH 2/2] cpu: Rename data types that conflict under ODR + +--- + src/cpu/core_dyn_x86.cpp | 4 ++-- + src/cpu/core_dyn_x86/cache.h | 2 +- + src/cpu/core_dyn_x86/decoder.h | 10 +++++----- + src/cpu/core_dyn_x86/risc_x64.h | 12 ++++++------ + src/cpu/core_dyn_x86/risc_x86.h | 8 ++++---- + src/cpu/core_dyn_x86/string.h | 4 ++-- + src/cpu/core_dynrec.cpp | 10 +++++----- + src/cpu/core_dynrec/cache.h | 2 +- + src/cpu/core_dynrec/decoder_basic.h | 10 +++++----- + src/cpu/core_normal/string.h | 4 ++-- + 10 files changed, 33 insertions(+), 33 deletions(-) + +diff --git a/src/cpu/core_dyn_x86.cpp b/src/cpu/core_dyn_x86.cpp +index 27c3dab5a6c..63beea5d495 100644 +--- a/src/cpu/core_dyn_x86.cpp ++++ b/src/cpu/core_dyn_x86.cpp +@@ -98,7 +98,7 @@ enum BranchTypes { + }; + + +-enum BlockReturn { ++enum BlockReturnDynX86 { + BR_Normal=0, + BR_Cycles, + BR_Link1,BR_Link2, +@@ -363,7 +363,7 @@ Bits CPU_Core_Dyn_X86_Run(void) { + run_block: + cache.block.running=0; + core_dyn.pagefault = false; +- BlockReturn ret=gen_runcode((uint8_t*)cache_rwtox(block->cache.start)); ++ BlockReturnDynX86 ret=gen_runcode((uint8_t*)cache_rwtox(block->cache.start)); + + if (sizeof(CPU_Cycles) > 4) { + // HACK: All dynrec cores for each processor assume CPU_Cycles is 32-bit wide. +diff --git a/src/cpu/core_dyn_x86/cache.h b/src/cpu/core_dyn_x86/cache.h +index c3d71212a8b..bf7d557306b 100644 +--- a/src/cpu/core_dyn_x86/cache.h ++++ b/src/cpu/core_dyn_x86/cache.h +@@ -495,7 +495,7 @@ static INLINE void cache_addq(uint64_t val) { + cache.pos=pos; + } + +-static void gen_return(BlockReturn retcode); ++static void gen_return(BlockReturnDynX86 retcode); + + static uint8_t * cache_code_start_ptr=NULL; + static uint8_t * cache_code=NULL; +diff --git a/src/cpu/core_dyn_x86/decoder.h b/src/cpu/core_dyn_x86/decoder.h +index 61dadd9083e..5f0691fa125 100644 +--- a/src/cpu/core_dyn_x86/decoder.h ++++ b/src/cpu/core_dyn_x86/decoder.h +@@ -42,7 +42,7 @@ union pagefault_restore { + uint32_t dword; + }; + +-static struct DynDecode { ++static struct DynDecodeDynX86 { + PhysPt code; + PhysPt code_start; + PhysPt eip_location; +@@ -360,11 +360,11 @@ static INLINE void dyn_set_eip_last(void) { + } + + +-enum save_info_type {db_exception, cycle_check, normal, fpu_restore, trap, page_fault}; ++enum save_info_type_dynx86 {db_exception, cycle_check, normal, fpu_restore, trap, page_fault}; + + + static struct { +- save_info_type type; ++ save_info_type_dynx86 type; + DynState state; + uint8_t * branch_pos; + uint32_t eip_change; +@@ -379,7 +379,7 @@ static struct { + Bitu used_save_info=0; + + +-static BlockReturn DynRunException(uint32_t eip_add,uint32_t cycle_sub,uint32_t dflags) { ++static BlockReturnDynX86 DynRunException(uint32_t eip_add,uint32_t cycle_sub,uint32_t dflags) { + reg_flags=(dflags&FMASK_TEST) | (reg_flags&(~FMASK_TEST)); + reg_eip+=eip_add; + CPU_Cycles-=cycle_sub; +@@ -392,7 +392,7 @@ static BlockReturn DynRunException(uint32_t eip_add,uint32_t cycle_sub,uint32_t + return BR_Normal; + } + +-static BlockReturn DynRunPageFault(uint32_t eip_add,uint32_t cycle_sub,uint32_t pf_restore,uint32_t dflags) { ++static BlockReturnDynX86 DynRunPageFault(uint32_t eip_add,uint32_t cycle_sub,uint32_t pf_restore,uint32_t dflags) { + pagefault_restore pf_restore_struct; + pf_restore_struct.dword = pf_restore; + reg_flags=(dflags&FMASK_TEST) | (reg_flags&(~FMASK_TEST)); +diff --git a/src/cpu/core_dyn_x86/risc_x64.h b/src/cpu/core_dyn_x86/risc_x64.h +index b1f660ca0f8..0c7d21ff270 100644 +--- a/src/cpu/core_dyn_x86/risc_x64.h ++++ b/src/cpu/core_dyn_x86/risc_x64.h +@@ -269,13 +269,13 @@ class GenReg { + } + }; + +-static BlockReturn gen_runcodeInit(uint8_t *code); +-static BlockReturn (*gen_runcode)(uint8_t *code) = gen_runcodeInit; ++static BlockReturnDynX86 gen_runcodeInit(uint8_t *code); ++static BlockReturnDynX86 (*gen_runcode)(uint8_t *code) = gen_runcodeInit; + +-static BlockReturn gen_runcodeInit(uint8_t *code) { ++static BlockReturnDynX86 gen_runcodeInit(uint8_t *code) { + uint8_t* oldpos = cache.pos; + cache.pos = &cache_code_link_blocks[128]; +- gen_runcode = (BlockReturn(*)(uint8_t*))cache_rwtox(cache.pos); ++ gen_runcode = (BlockReturnDynX86(*)(uint8_t*))cache_rwtox(cache.pos); + + opcode(5).Emit8Reg(0x50); // push rbp + opcode(15).Emit8Reg(0x50); // push r15 +@@ -1235,7 +1235,7 @@ static void gen_test_host_byte(void * data, uint8_t imm) { + opcode(0).setimm(imm,1).setabsaddr(data).Emit8(0xF6); // test byte[], uint8_t + } + +-static void gen_return(BlockReturn retcode) { ++static void gen_return(BlockReturnDynX86 retcode) { + gen_protectflags(); + opcode(1).setea(4,-1,0,CALLSTACK).Emit8(0x8B); // mov ecx, [rsp+8/40] + opcode(0).set64().setrm(4).setimm(CALLSTACK+8,1).Emit8(0x83); // add rsp,16/48 +@@ -1247,7 +1247,7 @@ static void gen_return(BlockReturn retcode) { + opcode(4).setea(4,-1,0,CALLSTACK-8).Emit8(0xFF); // jmp [rsp+CALLSTACK-8] + } + +-static void gen_return_fast(BlockReturn retcode,bool ret_exception=false) { ++static void gen_return_fast(BlockReturnDynX86 retcode,bool ret_exception=false) { + if (GCC_UNLIKELY(x64gen.flagsactive)) IllegalOption("gen_return_fast"); + opcode(1).setabsaddr(®_flags).Emit8(0x8B); // mov ECX, [cpu_regs.flags] + if (!ret_exception) { +diff --git a/src/cpu/core_dyn_x86/risc_x86.h b/src/cpu/core_dyn_x86/risc_x86.h +index 8d0b2174712..29e62678577 100644 +--- a/src/cpu/core_dyn_x86/risc_x86.h ++++ b/src/cpu/core_dyn_x86/risc_x86.h +@@ -84,8 +84,8 @@ class GenReg { + } + }; + +-static BlockReturn gen_runcode(uint8_t * code) { +- BlockReturn retval; ++static BlockReturnDynX86 gen_runcode(uint8_t * code) { ++ BlockReturnDynX86 retval; + #if defined (_MSC_VER) + __asm { + /* Prepare the flags */ +@@ -1072,7 +1072,7 @@ static void gen_test_host_byte(void * data, uint8_t imm) { + cache_addb(imm); + } + +-static void gen_return(BlockReturn retcode) { ++static void gen_return(BlockReturnDynX86 retcode) { + gen_protectflags(); + cache_addb(0x59); //POP ECX, the flags + if (retcode==0) cache_addw(0xc033); //MOV EAX, 0 +@@ -1083,7 +1083,7 @@ static void gen_return(BlockReturn retcode) { + cache_addb(0xc3); //RET + } + +-static void gen_return_fast(BlockReturn retcode,bool ret_exception=false) { ++static void gen_return_fast(BlockReturnDynX86 retcode,bool ret_exception=false) { + if (GCC_UNLIKELY(x86gen.flagsactive)) IllegalOption("gen_return_fast"); + cache_addw(0x0d8b); //MOV ECX, the flags + cache_addd((uintptr_t)&cpu_regs.flags); +diff --git a/src/cpu/core_dyn_x86/string.h b/src/cpu/core_dyn_x86/string.h +index 01fbef2b412..f5f7cca5c70 100644 +--- a/src/cpu/core_dyn_x86/string.h ++++ b/src/cpu/core_dyn_x86/string.h +@@ -18,7 +18,7 @@ + + #include "inout.h" + +-enum STRING_OP { ++enum STRING_OP_DYNX86 { + STR_OUTSB=0,STR_OUTSW,STR_OUTSD, + STR_INSB=4,STR_INSW,STR_INSD, + STR_MOVSB=8,STR_MOVSW,STR_MOVSD, +@@ -28,7 +28,7 @@ enum STRING_OP { + STR_CMPSB=24,STR_CMPSW,STR_CMPSD + }; + +-static void dyn_string(STRING_OP op) { ++static void dyn_string(STRING_OP_DYNX86 op) { + DynReg * si_base=decode.segprefix ? decode.segprefix : DREG(DS); + DynReg * di_base=DREG(ES); + DynReg * tmp_reg;bool usesi;bool usedi;bool cmp=false; +diff --git a/src/cpu/core_dynrec.cpp b/src/cpu/core_dynrec.cpp +index a0097db347f..af275cbefa9 100644 +--- a/src/cpu/core_dynrec.cpp ++++ b/src/cpu/core_dynrec.cpp +@@ -97,7 +97,7 @@ + #define DRCD_REG_WORD(reg,dwrd) ((dwrd)?((void*)(&cpu_regs.regs[reg].dword[DW_INDEX])):((void*)(&cpu_regs.regs[reg].word[W_INDEX]))) + + +-enum BlockReturn { ++enum BlockReturnDynRec { + BR_Normal=0, + BR_Cycles, + BR_Link1,BR_Link2, +@@ -120,7 +120,7 @@ static void IllegalOptionDynrec(const char* msg) { + } + + static struct { +- BlockReturn (*runcode)(uint8_t*); // points to code that can start a block ++ BlockReturnDynRec (*runcode)(uint8_t*); // points to code that can start a block + Bitu callback; // the occurred callback + Bitu readdata; // spare space used when reading from memory + uint32_t protected_regs[8]; // space to save/restore register values +@@ -192,7 +192,7 @@ static bool winrt_warning = true; + #endif + + +-CacheBlockDynRec * LinkBlocks(BlockReturn ret) { ++CacheBlockDynRec * LinkBlocks(BlockReturnDynRec ret) { + CacheBlockDynRec * block=NULL; + // the last instruction was a control flow modifying instruction + uint32_t temp_ip=SegPhys(cs)+reg_eip; +@@ -307,8 +307,8 @@ Bits CPU_Core_Dynrec_Run(void) { + run_block: + cache.block.running=0; + // now we're ready to run the dynamic code block +-// BlockReturn ret=((BlockReturn (*)(void))(block->cache.start))(); +- BlockReturn ret=core_dynrec.runcode(block->cache.xstart); ++// BlockReturnDynRec ret=((BlockReturnDynRec (*)(void))(block->cache.start))(); ++ BlockReturnDynRec ret=core_dynrec.runcode(block->cache.xstart); + + if (sizeof(CPU_Cycles) > 4) { + // HACK: All dynrec cores for each processor assume CPU_Cycles is 32-bit wide. +diff --git a/src/cpu/core_dynrec/cache.h b/src/cpu/core_dynrec/cache.h +index 7c6fb3c0755..32598b899d8 100644 +--- a/src/cpu/core_dynrec/cache.h ++++ b/src/cpu/core_dynrec/cache.h +@@ -601,7 +601,7 @@ static INLINE void cache_addq(uint64_t val) { + } + + +-static void dyn_return(BlockReturn retcode,bool ret_exception); ++static void dyn_return(BlockReturnDynRec retcode,bool ret_exception); + static void dyn_run_code(void); + + static bool cache_initialized = false; +diff --git a/src/cpu/core_dynrec/decoder_basic.h b/src/cpu/core_dynrec/decoder_basic.h +index ca7f0c8bc2a..6b468223e25 100644 +--- a/src/cpu/core_dynrec/decoder_basic.h ++++ b/src/cpu/core_dynrec/decoder_basic.h +@@ -93,7 +93,7 @@ static DualOps grp1_table[8]={ + + + // decoding information used during translation of a code block +-static struct DynDecode { ++static struct DynDecodeDynRec { + PhysPt code; // pointer to next byte in the instruction stream + PhysPt code_start; // pointer to the start of the current code block + PhysPt op_start; // pointer to the start of the current instruction +@@ -614,11 +614,11 @@ template <typename T> static DRC_PTR_SIZE_IM INLINE gen_call_function_mm(const T + + + +-enum save_info_type {db_exception, cycle_check, string_break, trap}; ++enum save_info_type_dynrec {db_exception, cycle_check, string_break, trap}; + + + // function that is called on exceptions +-static BlockReturn DynRunException(uint32_t eip_add,uint32_t cycle_sub) { ++static BlockReturnDynRec DynRunException(uint32_t eip_add,uint32_t cycle_sub) { + reg_eip+=eip_add; + CPU_Cycles-=cycle_sub; + if (cpu.exception.which==SMC_CURRENT_BLOCK) return BR_SMCBlock; +@@ -630,7 +630,7 @@ static BlockReturn DynRunException(uint32_t eip_add,uint32_t cycle_sub) { + // array with information about code that is generated at the + // end of a cache block because it is rarely reached (like exceptions) + static struct { +- save_info_type type; ++ save_info_type_dynrec type; + DRC_PTR_SIZE_IM branch_pos; + uint32_t eip_change; + Bitu cycles; +@@ -640,7 +640,7 @@ Bitu used_save_info_dynrec=0; + + + // return from current block, with returncode +-static void dyn_return(BlockReturn retcode,bool ret_exception=false) { ++static void dyn_return(BlockReturnDynRec retcode,bool ret_exception=false) { + if (!ret_exception) { + gen_mov_dword_to_reg_imm(FC_RETOP,retcode); + } +diff --git a/src/cpu/core_normal/string.h b/src/cpu/core_normal/string.h +index a796ba2fc2a..4daa8b508d8 100644 +--- a/src/cpu/core_normal/string.h ++++ b/src/cpu/core_normal/string.h +@@ -19,7 +19,7 @@ + #include "inout.h" + #include "logging.h" + +-enum STRING_OP { ++enum STRING_OP_NORMAL { + // simple string ops + R_OUTSB,R_OUTSW,R_OUTSD, + R_INSB, R_INSW, R_INSD, +@@ -35,7 +35,7 @@ enum STRING_OP { + + extern int cpu_rep_max; + +-void DoString(STRING_OP type) { ++void DoString(STRING_OP_NORMAL type) { + static PhysPt si_base,di_base; + static uint32_t si_index,di_index; + static uint32_t add_mask;
