commit: fa8ecf16250574ef198adbc79c902f35507e34a3 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Sat Sep 2 09:58:04 2023 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Sat Sep 2 09:58:04 2023 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=fa8ecf16
Linux patch 5.4.256 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> 0000_README | 4 ++ 1255_linux-5.4.256.patch | 97 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/0000_README b/0000_README index 250d3166..89c53712 100644 --- a/0000_README +++ b/0000_README @@ -1063,6 +1063,10 @@ Patch: 1254_linux-5.4.255.patch From: https://www.kernel.org Desc: Linux 5.4.255 +Patch: 1255_linux-5.4.256.patch +From: https://www.kernel.org +Desc: Linux 5.4.256 + Patch: 1500_XATTR_USER_PREFIX.patch From: https://bugs.gentoo.org/show_bug.cgi?id=470644 Desc: Support for namespace user.pax.* on tmpfs. diff --git a/1255_linux-5.4.256.patch b/1255_linux-5.4.256.patch new file mode 100644 index 00000000..f7216b6f --- /dev/null +++ b/1255_linux-5.4.256.patch @@ -0,0 +1,97 @@ +diff --git a/Makefile b/Makefile +index 041adebe7da2d..e5761a10f4a67 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + VERSION = 5 + PATCHLEVEL = 4 +-SUBLEVEL = 255 ++SUBLEVEL = 256 + EXTRAVERSION = + NAME = Kleptomaniac Octopus + +diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c +index e9ee9ab90a0c6..4ca2c28878e0f 100644 +--- a/arch/mips/alchemy/common/dbdma.c ++++ b/arch/mips/alchemy/common/dbdma.c +@@ -30,7 +30,6 @@ + * + */ + +-#include <linux/dma-map-ops.h> /* for dma_default_coherent */ + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/slab.h> +@@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + + /* +- * There is an erratum on certain Au1200/Au1550 revisions that could +- * result in "stale" data being DMA'ed. It has to do with the snoop +- * logic on the cache eviction buffer. dma_default_coherent is set +- * to false on these parts. ++ * There is an errata on the Au1200/Au1550 parts that could result ++ * in "stale" data being DMA'ed. It has to do with the snoop logic on ++ * the cache eviction buffer. DMA_NONCOHERENT is on by default for ++ * these parts. If it is fixed in the future, these dma_cache_inv will ++ * just be nothing more than empty macros. See io.h. + */ +- if (!dma_default_coherent) +- dma_cache_wback_inv(KSEG0ADDR(buf), nbytes); ++ dma_cache_wback_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + wmb(); /* drain writebuffer */ + dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); + ctp->chan_ptr->ddma_dbell = 0; +- wmb(); /* force doorbell write out to dma engine */ + + /* Get next descriptor pointer. */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); +@@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); + #endif + /* +- * There is an erratum on certain Au1200/Au1550 revisions that could +- * result in "stale" data being DMA'ed. It has to do with the snoop +- * logic on the cache eviction buffer. dma_default_coherent is set +- * to false on these parts. ++ * There is an errata on the Au1200/Au1550 parts that could result in ++ * "stale" data being DMA'ed. It has to do with the snoop logic on the ++ * cache eviction buffer. DMA_NONCOHERENT is on by default for these ++ * parts. If it is fixed in the future, these dma_cache_inv will just ++ * be nothing more than empty macros. See io.h. + */ +- if (!dma_default_coherent) +- dma_cache_inv(KSEG0ADDR(buf), nbytes); ++ dma_cache_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + wmb(); /* drain writebuffer */ + dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); + ctp->chan_ptr->ddma_dbell = 0; +- wmb(); /* force doorbell write out to dma engine */ + + /* Get next descriptor pointer. */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); +diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c +index f95fbdee6efe9..d2900689d642a 100644 +--- a/arch/powerpc/platforms/powermac/smp.c ++++ b/arch/powerpc/platforms/powermac/smp.c +@@ -660,13 +660,13 @@ static void smp_core99_gpio_tb_freeze(int freeze) + + #endif /* !CONFIG_PPC64 */ + +-/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ +-volatile static long int core99_l2_cache; +-volatile static long int core99_l3_cache; +- + static void core99_init_caches(int cpu) + { + #ifndef CONFIG_PPC64 ++ /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ ++ static long int core99_l2_cache; ++ static long int core99_l3_cache; ++ + if (!cpu_has_feature(CPU_FTR_L2CR)) + return; +
