commit: 31de670a01566db841c795577bbdc3f2a5d35f21 Author: Sam James <sam <AT> gentoo <DOT> org> AuthorDate: Mon Jan 8 08:10:06 2024 +0000 Commit: Sam James <sam <AT> gentoo <DOT> org> CommitDate: Mon Jan 8 08:10:06 2024 +0000 URL: https://gitweb.gentoo.org/proj/gcc-patches.git/commit/?id=31de670a
14.0.0: cut patchset 15 richi is back this week so this should be the last time we need to keep reverting these as the fixes are pending his review. Signed-off-by: Sam James <sam <AT> gentoo.org> ...le-end-explicitly-initialize-vec_stmts-PR.patch | 6 +- ...suite-un-xfail-TSVC-loops-that-check-for-.patch | 4 +- ..._Add_Advanced_SIMD_cbranch_implementation.patch | 341 +++++++++++++++++++++ ..._add_tests_for_early_break_vectorization.patch} | 14 +- ...64_add_implementation_for_vector_cbranch.patch} | 6 +- ...support_vectorization_of_loops_with_mult.patch} | 20 +- ...e-end-prevent-LIM-from-hoising-vector-co.patch} | 6 +- ...te_Add_more_pragma_novector_to_new_tests.patch} | 4 +- 14.0.0/gentoo/README.history | 11 + 9 files changed, 382 insertions(+), 30 deletions(-) diff --git a/14.0.0/gentoo/75_all_Revert-middle-end-explicitly-initialize-vec_stmts-PR.patch b/14.0.0/gentoo/75_all_Revert-middle-end-explicitly-initialize-vec_stmts-PR.patch index b113f1e..93bf96b 100644 --- a/14.0.0/gentoo/75_all_Revert-middle-end-explicitly-initialize-vec_stmts-PR.patch +++ b/14.0.0/gentoo/75_all_Revert-middle-end-explicitly-initialize-vec_stmts-PR.patch @@ -1,7 +1,7 @@ -From a648fe2c0121414ac82926e9f8a70b33e347b930 Mon Sep 17 00:00:00 2001 +From 0d9351ff8ab23e79edc7a468a255a7c009695f21 Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:10 +0000 -Subject: [PATCH 1/7] Revert "middle-end: explicitly initialize vec_stmts +Subject: [PATCH 1/8] Revert "middle-end: explicitly initialize vec_stmts [PR113132]" This reverts commit fd032cce216e003d58b2394f7e61b03dee27e81a. @@ -15,7 +15,7 @@ Signed-off-by: Sam James <[email protected]> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc -index f51ae3e719e7..88261a3a4f57 100644 +index a06771611ac8..2bd96b56006a 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -6207,7 +6207,7 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, diff --git a/14.0.0/gentoo/76_all_Revert-testsuite-un-xfail-TSVC-loops-that-check-for-.patch b/14.0.0/gentoo/76_all_Revert-testsuite-un-xfail-TSVC-loops-that-check-for-.patch index 1e4b825..d22a7ae 100644 --- a/14.0.0/gentoo/76_all_Revert-testsuite-un-xfail-TSVC-loops-that-check-for-.patch +++ b/14.0.0/gentoo/76_all_Revert-testsuite-un-xfail-TSVC-loops-that-check-for-.patch @@ -1,7 +1,7 @@ -From 846bfbdd30d437e40e10ce8bcd896f263436dfc1 Mon Sep 17 00:00:00 2001 +From 21f952dd33ae6037ff1a18cfe1c52dcc9becce19 Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:12 +0000 -Subject: [PATCH 2/7] Revert "testsuite: un-xfail TSVC loops that check for +Subject: [PATCH 2/8] Revert "testsuite: un-xfail TSVC loops that check for exit control flow vectorization" This reverts commit a657c7e3518fcfc796f223d47385cad5e97dc9a5. diff --git a/14.0.0/gentoo/77_all_Revert_arm_Add_Advanced_SIMD_cbranch_implementation.patch b/14.0.0/gentoo/77_all_Revert_arm_Add_Advanced_SIMD_cbranch_implementation.patch new file mode 100644 index 0000000..e284b9d --- /dev/null +++ b/14.0.0/gentoo/77_all_Revert_arm_Add_Advanced_SIMD_cbranch_implementation.patch @@ -0,0 +1,341 @@ +From f7dfd5052edeaa7f433bc296fd3c8b9c5239edb3 Mon Sep 17 00:00:00 2001 +From: Sam James <[email protected]> +Date: Mon, 8 Jan 2024 07:09:10 +0000 +Subject: [PATCH 3/8] Revert "arm: Add Advanced SIMD cbranch implementation" + +This reverts commit d9dd04f9f17e36854387899eb630c64a0c8d1a17. + +Bug: https://gcc.gnu.org/PR113135 +Bug: https://gcc.gnu.org/PR113136 +Bug: https://gcc.gnu.org/PR113137 +Signed-off-by: Sam James <[email protected]> +--- + gcc/config/arm/neon.md | 49 ------- + .../gcc.dg/vect/vect-early-break_2.c | 2 +- + .../gcc.dg/vect/vect-early-break_7.c | 2 +- + .../gcc.dg/vect/vect-early-break_75.c | 2 +- + .../gcc.dg/vect/vect-early-break_77.c | 2 +- + .../gcc.dg/vect/vect-early-break_82.c | 2 +- + .../gcc.dg/vect/vect-early-break_88.c | 2 +- + .../gcc.target/arm/vect-early-break-cbranch.c | 138 ------------------ + gcc/testsuite/lib/target-supports.exp | 7 - + 9 files changed, 6 insertions(+), 200 deletions(-) + delete mode 100644 gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c + +diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md +index bb6e28ff4e74..91ca7e804555 100644 +--- a/gcc/config/arm/neon.md ++++ b/gcc/config/arm/neon.md +@@ -408,55 +408,6 @@ (define_insn "vec_extract<mode><V_elem_l>" + [(set_attr "type" "neon_store1_one_lane<q>,neon_to_gp<q>")] + ) + +-;; Patterns comparing two vectors and conditionally jump. +-;; Avdanced SIMD lacks a vector != comparison, but this is a quite common +-;; operation. To not pay the penalty for inverting == we can map our any +-;; comparisons to all i.e. any(~x) => all(x). +-;; +-;; However unlike the AArch64 version, we can't optimize this further as the +-;; chain is too long for combine due to these being unspecs so it doesn't fold +-;; the operation to something simpler. +-(define_expand "cbranch<mode>4" +- [(set (pc) (if_then_else +- (match_operator 0 "expandable_comparison_operator" +- [(match_operand:VDQI 1 "register_operand") +- (match_operand:VDQI 2 "reg_or_zero_operand")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] +- "TARGET_NEON" +-{ +- rtx mask = operands[1]; +- +- /* If comparing against a non-zero vector we have to do a comparison first +- so we can have a != 0 comparison with the result. */ +- if (operands[2] != CONST0_RTX (<MODE>mode)) +- { +- mask = gen_reg_rtx (<MODE>mode); +- emit_insn (gen_xor<mode>3 (mask, operands[1], operands[2])); +- } +- +- /* For 128-bit vectors we need an additional reductions. */ +- if (known_eq (128, GET_MODE_BITSIZE (<MODE>mode))) +- { +- /* Always reduce using a V4SI. */ +- rtx op1 = lowpart_subreg (V4SImode, mask, <MODE>mode); +- mask = gen_reg_rtx (V2SImode); +- rtx low = gen_reg_rtx (V2SImode); +- rtx high = gen_reg_rtx (V2SImode); +- emit_insn (gen_neon_vget_lowv4si (low, op1)); +- emit_insn (gen_neon_vget_highv4si (high, op1)); +- emit_insn (gen_neon_vpumaxv2si (mask, low, high)); +- } +- +- rtx op1 = lowpart_subreg (V2SImode, mask, GET_MODE (mask)); +- emit_insn (gen_neon_vpumaxv2si (op1, op1, op1)); +- +- rtx val = gen_reg_rtx (SImode); +- emit_move_insn (val, gen_lowpart (SImode, mask)); +- emit_jump_insn (gen_cbranch_cc (operands[0], val, const0_rtx, operands[3])); +- DONE; +-}) +- + ;; This pattern is renamed from "vec_extract<mode><V_elem_l>" to + ;; "neon_vec_extract<mode><V_elem_l>" and this pattern is called + ;; by define_expand in vec-common.md file. +diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_2.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_2.c +index dec0b492ab88..5c32bf94409e 100644 +--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_2.c ++++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_2.c +@@ -5,7 +5,7 @@ + + /* { dg-additional-options "-Ofast" } */ + +-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "arm*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + + #include <complex.h> + +diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_7.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_7.c +index d218a0686719..8c86c5034d75 100644 +--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_7.c ++++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_7.c +@@ -5,7 +5,7 @@ + + /* { dg-additional-options "-Ofast" } */ + +-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "arm*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + + #include <complex.h> + +diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_75.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_75.c +index 9dcc3372acd6..ed27f8635730 100644 +--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_75.c ++++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_75.c +@@ -3,7 +3,7 @@ + /* { dg-require-effective-target vect_int } */ + + /* { dg-additional-options "-O3" } */ +-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "x86_64-*-* i?86-*-* arm*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "x86_64-*-* i?86-*-*" } } } } */ + + #include <limits.h> + #include <assert.h> +diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_77.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_77.c +index 9fa7e6948ebf..225106aab0a3 100644 +--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_77.c ++++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_77.c +@@ -3,7 +3,7 @@ + /* { dg-require-effective-target vect_int } */ + + /* { dg-additional-options "-O3" } */ +-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "arm*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + + #include "tree-vect.h" + +diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_82.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_82.c +index 7cd21d33485f..0e9b2d8d385c 100644 +--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_82.c ++++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_82.c +@@ -5,7 +5,7 @@ + + /* { dg-additional-options "-Ofast" } */ + +-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "arm*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + + #include <complex.h> + +diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_88.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_88.c +index 59ed57c5fb5f..b392dd465539 100644 +--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_88.c ++++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_88.c +@@ -3,7 +3,7 @@ + /* { dg-require-effective-target vect_int } */ + + /* { dg-additional-options "-Ofast --param vect-partial-vector-usage=2" } */ +-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { ! "arm*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + + #include "tree-vect.h" + +diff --git a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c +deleted file mode 100644 +index f57bbd8be428..000000000000 +--- a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c ++++ /dev/null +@@ -1,138 +0,0 @@ +-/* { dg-do compile } */ +-/* { dg-require-effective-target vect_early_break } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-require-effective-target arm32 } */ +-/* { dg-options "-O3 -march=armv8-a+simd -mfpu=auto -mfloat-abi=hard -fno-schedule-insns -fno-reorder-blocks -fno-schedule-insns2" } */ +-/* { dg-final { check-function-bodies "**" "" "" } } */ +- +-#define N 640 +-int a[N] = {0}; +-int b[N] = {0}; +- +-/* +-** f1: +-** ... +-** vcgt.s32 q[0-9]+, q[0-9]+, #0 +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vmov r[0-9]+, s[0-9]+ @ int +-** cmp r[0-9]+, #0 +-** bne \.L[0-9]+ +-** ... +-*/ +-void f1 () +-{ +- for (int i = 0; i < N; i++) +- { +- b[i] += a[i]; +- if (a[i] > 0) +- break; +- } +-} +- +-/* +-** f2: +-** ... +-** vcge.s32 q[0-9]+, q[0-9]+, #0 +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vmov r[0-9]+, s[0-9]+ @ int +-** cmp r[0-9]+, #0 +-** bne \.L[0-9]+ +-** ... +-*/ +-void f2 () +-{ +- for (int i = 0; i < N; i++) +- { +- b[i] += a[i]; +- if (a[i] >= 0) +- break; +- } +-} +- +-/* +-** f3: +-** ... +-** vceq.i32 q[0-9]+, q[0-9]+, #0 +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vmov r[0-9]+, s[0-9]+ @ int +-** cmp r[0-9]+, #0 +-** bne \.L[0-9]+ +-** ... +-*/ +-void f3 () +-{ +- for (int i = 0; i < N; i++) +- { +- b[i] += a[i]; +- if (a[i] == 0) +- break; +- } +-} +- +-/* +-** f4: +-** ... +-** vceq.i32 q[0-9]+, q[0-9]+, #0 +-** vmvn q[0-9]+, q[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vmov r[0-9]+, s[0-9]+ @ int +-** cmp r[0-9]+, #0 +-** bne \.L[0-9]+ +-** ... +-*/ +-void f4 () +-{ +- for (int i = 0; i < N; i++) +- { +- b[i] += a[i]; +- if (a[i] != 0) +- break; +- } +-} +- +-/* +-** f5: +-** ... +-** vclt.s32 q[0-9]+, q[0-9]+, #0 +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vmov r[0-9]+, s[0-9]+ @ int +-** cmp r[0-9]+, #0 +-** bne \.L[0-9]+ +-** ... +-*/ +-void f5 () +-{ +- for (int i = 0; i < N; i++) +- { +- b[i] += a[i]; +- if (a[i] < 0) +- break; +- } +-} +- +-/* +-** f6: +-** ... +-** vcle.s32 q[0-9]+, q[0-9]+, #0 +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ +-** vmov r[0-9]+, s[0-9]+ @ int +-** cmp r[0-9]+, #0 +-** bne \.L[0-9]+ +-** ... +-*/ +-void f6 () +-{ +- for (int i = 0; i < N; i++) +- { +- b[i] += a[i]; +- if (a[i] <= 0) +- break; +- } +-} +- +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index b27c30b8c51b..d65953158651 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -4069,7 +4069,6 @@ proc check_effective_target_vect_early_break { } { + return [check_cached_effective_target_indexed vect_early_break { + expr { + [istarget aarch64*-*-*] +- || [check_effective_target_arm_v8_neon_ok] + || [check_effective_target_sse4] + }}] + } +@@ -4083,7 +4082,6 @@ proc check_effective_target_vect_early_break_hw { } { + return [check_cached_effective_target_indexed vect_early_break_hw { + expr { + [istarget aarch64*-*-*] +- || [check_effective_target_arm_v8_neon_hw] + || [check_sse4_hw_available] + }}] + } +@@ -4093,11 +4091,6 @@ proc add_options_for_vect_early_break { flags } { + return "$flags" + } + +- if { [check_effective_target_arm_v8_neon_ok] } { +- global et_arm_v8_neon_flags +- return "$flags $et_arm_v8_neon_flags -march=armv8-a" +- } +- + if { [check_effective_target_sse4] } { + return "$flags -msse4.1" + } +-- +2.43.0 + diff --git a/14.0.0/gentoo/77_all_Revert-testsuite-Add-tests-for-early-break-vectoriza.patch b/14.0.0/gentoo/78_all_Revert_testsuite_add_tests_for_early_break_vectorization.patch similarity index 99% rename from 14.0.0/gentoo/77_all_Revert-testsuite-Add-tests-for-early-break-vectoriza.patch rename to 14.0.0/gentoo/78_all_Revert_testsuite_add_tests_for_early_break_vectorization.patch index f4e6b84..6fbdd54 100644 --- a/14.0.0/gentoo/77_all_Revert-testsuite-Add-tests-for-early-break-vectoriza.patch +++ b/14.0.0/gentoo/78_all_Revert_testsuite_add_tests_for_early_break_vectorization.patch @@ -1,7 +1,7 @@ -From 3283ec82265c4bd51a2d113ebe44310169614650 Mon Sep 17 00:00:00 2001 +From 2fe83ac81d631810a520e5938224c5d10ffbc269 Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:13 +0000 -Subject: [PATCH 3/7] Revert "testsuite: Add tests for early break +Subject: [PATCH 4/8] Revert "testsuite: Add tests for early break vectorization" This reverts commit c5232ec14937a34e599e9e386a5975fab9a5e283. @@ -232,10 +232,10 @@ Signed-off-by: Sam James <[email protected]> delete mode 100644 gcc/testsuite/gcc.dg/vect/vect-early-break_93.c diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi -index bd62b21f3b72..4be67daedb20 100644 +index 3a394e7739b6..35da6c11a5a9 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi -@@ -1636,14 +1636,6 @@ Target supports hardware vectors of @code{float} when +@@ -1645,14 +1645,6 @@ Target supports hardware vectors of @code{float} when @option{-funsafe-math-optimizations} is not in effect. This implies @code{vect_float}. @@ -250,7 +250,7 @@ index bd62b21f3b72..4be67daedb20 100644 @item vect_int Target supports hardware vectors of @code{int}. -@@ -3213,11 +3205,6 @@ instructions, if any. +@@ -3222,11 +3214,6 @@ instructions, if any. @item tls Add the target-specific flags needed to use thread-local storage. @@ -4902,10 +4902,10 @@ index 656a7788896d..000000000000 - return 0; -} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index 05fc417877bc..7f13ff0ca565 100644 +index d65953158651..dc8e0bc7c2bd 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp -@@ -4050,44 +4050,6 @@ proc check_effective_target_vect_int { } { +@@ -4060,44 +4060,6 @@ proc check_effective_target_vect_int { } { }}] } diff --git a/14.0.0/gentoo/78_all_Revert-AArch64-Add-implementation-for-vector-cbranch.patch b/14.0.0/gentoo/79_all_Revert_AArch64_add_implementation_for_vector_cbranch.patch similarity index 97% rename from 14.0.0/gentoo/78_all_Revert-AArch64-Add-implementation-for-vector-cbranch.patch rename to 14.0.0/gentoo/79_all_Revert_AArch64_add_implementation_for_vector_cbranch.patch index 42a06f1..3a6aa30 100644 --- a/14.0.0/gentoo/78_all_Revert-AArch64-Add-implementation-for-vector-cbranch.patch +++ b/14.0.0/gentoo/79_all_Revert_AArch64_add_implementation_for_vector_cbranch.patch @@ -1,7 +1,7 @@ -From d85db7a7354005e99a143453e103f784614cef0e Mon Sep 17 00:00:00 2001 +From 31b1a8e79e86712d87ebe8de201636c8bd83a6be Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:13 +0000 -Subject: [PATCH 4/7] Revert "AArch64: Add implementation for vector cbranch +Subject: [PATCH 5/8] Revert "AArch64: Add implementation for vector cbranch for Advanced SIMD" This reverts commit 1bcc07aeb47c0ed7eb50eac8a4e057d6336669ab. @@ -19,7 +19,7 @@ Signed-off-by: Sam James <[email protected]> delete mode 100644 gcc/testsuite/gcc.target/aarch64/vect-early-break-cbranch.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md -index f88b5bde254e..7c5fd4238357 100644 +index 3cd184f46fa9..8aa55c641e1c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3885,48 +3885,6 @@ (define_expand "vcond_mask_<mode><v_int_equiv>" diff --git a/14.0.0/gentoo/79_all_Revert-middle-end-Support-vectorization-of-loops-wit.patch b/14.0.0/gentoo/80_all_Revert_middle-end_support_vectorization_of_loops_with_mult.patch similarity index 99% rename from 14.0.0/gentoo/79_all_Revert-middle-end-Support-vectorization-of-loops-wit.patch rename to 14.0.0/gentoo/80_all_Revert_middle-end_support_vectorization_of_loops_with_mult.patch index 549472b..ac87127 100644 --- a/14.0.0/gentoo/79_all_Revert-middle-end-Support-vectorization-of-loops-wit.patch +++ b/14.0.0/gentoo/80_all_Revert_middle-end_support_vectorization_of_loops_with_mult.patch @@ -1,7 +1,7 @@ -From 3385d9b56e25b75a2e0fe3286b329b82b703362d Mon Sep 17 00:00:00 2001 +From 884068ec19c846246ab55b4820fd2badca329339 Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:14 +0000 -Subject: [PATCH 5/7] Revert "middle-end: Support vectorization of loops with +Subject: [PATCH 6/8] Revert "middle-end: Support vectorization of loops with multiple exits." This reverts commit 01f4251b8775c832a92d55e2df57c9ac72eaceef. @@ -22,7 +22,7 @@ Signed-off-by: Sam James <[email protected]> 8 files changed, 233 insertions(+), 1330 deletions(-) diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc -index 9638d3cc869a..e169413bb44c 100644 +index 8e79362f96ab..bb87db382086 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -844,7 +844,7 @@ idx_within_array_bound (tree ref, tree *idx, void *dta) @@ -35,7 +35,7 @@ index 9638d3cc869a..e169413bb44c 100644 { class loop *loop = loop_containing_stmt (stmt); diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc -index 3d9673fb0b58..d5c9c4a11c2e 100644 +index 752c34c26e9b..290303f198b5 100644 --- a/gcc/tree-vect-data-refs.cc +++ b/gcc/tree-vect-data-refs.cc @@ -613,238 +613,6 @@ vect_analyze_data_ref_dependence (struct data_dependence_relation *ddr, @@ -290,7 +290,7 @@ index 3d9673fb0b58..d5c9c4a11c2e 100644 } diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc -index 295e1c916874..bcd90a331f5a 100644 +index 9330183bfb9e..9182192710eb 100644 --- a/gcc/tree-vect-loop-manip.cc +++ b/gcc/tree-vect-loop-manip.cc @@ -448,20 +448,6 @@ vect_adjust_loop_lens_control (tree iv_type, gimple_seq *seq, @@ -881,7 +881,7 @@ index 295e1c916874..bcd90a331f5a 100644 for (gsi = gsi_start_phis (merge_bb); !gsi_end_p (gsi); diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc -index 88261a3a4f57..7a3db5f098ba 100644 +index 2bd96b56006a..5d5f57561741 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -1040,7 +1040,6 @@ _loop_vec_info::_loop_vec_info (class loop *loop_in, vec_info_shared *shared) @@ -1577,7 +1577,7 @@ index 88261a3a4f57..7a3db5f098ba 100644 below. */ if (!loop_vinfo->slp_instances.is_empty ()) diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc -index 2053673debe9..696b70b76a82 100644 +index f1a95ef34b93..b0ceb1007bd4 100644 --- a/gcc/tree-vect-patterns.cc +++ b/gcc/tree-vect-patterns.cc @@ -132,7 +132,6 @@ vect_init_pattern_stmt (vec_info *vinfo, gimple *pattern_stmt, @@ -1827,7 +1827,7 @@ index 2053673debe9..696b70b76a82 100644 if (STMT_VINFO_REDUC_IDX (orig_stmt_info_saved) != -1) { diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc -index 1333d8934783..e9ff728dfd40 100644 +index bdbf08c9d298..267bb444c284 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -342,7 +342,6 @@ is_simple_and_all_uses_invariant (stmt_vec_info stmt_info, @@ -2305,7 +2305,7 @@ index 1333d8934783..e9ff728dfd40 100644 scalar_type = TREE_TYPE (DR_REF (dr)); else if (gimple_call_internal_p (stmt, IFN_MASK_STORE)) diff --git a/gcc/tree-vectorizer.cc b/gcc/tree-vectorizer.cc -index 8b495fc7ca13..d97e2b54c25a 100644 +index 9001b738bf31..8e34549b1775 100644 --- a/gcc/tree-vectorizer.cc +++ b/gcc/tree-vectorizer.cc @@ -1381,9 +1381,7 @@ pass_vectorize::execute (function *fun) @@ -2320,7 +2320,7 @@ index 8b495fc7ca13..d97e2b54c25a 100644 edge entry = EDGE_PRED (loop_preheader_edge (loop)->src, 0); do_rpo_vn (fun, entry, exit_bbs); diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h -index 785fc99ca27a..1810833a324a 100644 +index db44d730b702..62c9818ee0dd 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -66,7 +66,6 @@ enum vect_def_type { diff --git a/14.0.0/gentoo/80_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch b/14.0.0/gentoo/81_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch similarity index 90% rename from 14.0.0/gentoo/80_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch rename to 14.0.0/gentoo/81_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch index 2473ce4..42c1f15 100644 --- a/14.0.0/gentoo/80_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch +++ b/14.0.0/gentoo/81_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch @@ -1,7 +1,7 @@ -From eccc75285320e5c4a4c21ec48ac2ab8bf8ca3580 Mon Sep 17 00:00:00 2001 +From 596b268da13ffc54200075212eadba01ac73a847 Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:15 +0000 -Subject: [PATCH 6/7] Revert "middle-end: prevent LIM from hoising vector +Subject: [PATCH 7/8] Revert "middle-end: prevent LIM from hoising vector compares from gconds if target does not support it." This reverts commit f1dcc0fe371e3cb10d2cbe3f6c88db6f72edddda. @@ -15,7 +15,7 @@ Signed-off-by: Sam James <[email protected]> 1 file changed, 13 deletions(-) diff --git a/gcc/tree-ssa-loop-im.cc b/gcc/tree-ssa-loop-im.cc -index 2ebf6d6548c4..396963b6754c 100644 +index f3fda2bd7ce1..dd2aacaeee43 100644 --- a/gcc/tree-ssa-loop-im.cc +++ b/gcc/tree-ssa-loop-im.cc @@ -48,8 +48,6 @@ along with GCC; see the file COPYING3. If not see diff --git a/14.0.0/gentoo/81_all_Revert-testsuite-Add-more-pragma-novector-to-new-tes.patch b/14.0.0/gentoo/82_all_testsuite_Add_more_pragma_novector_to_new_tests.patch similarity index 99% rename from 14.0.0/gentoo/81_all_Revert-testsuite-Add-more-pragma-novector-to-new-tes.patch rename to 14.0.0/gentoo/82_all_testsuite_Add_more_pragma_novector_to_new_tests.patch index 88e414e..0586a1c 100644 --- a/14.0.0/gentoo/81_all_Revert-testsuite-Add-more-pragma-novector-to-new-tes.patch +++ b/14.0.0/gentoo/82_all_testsuite_Add_more_pragma_novector_to_new_tests.patch @@ -1,7 +1,7 @@ -From aa2a8d5c6f86e0b61e92b1ca02859cd480647f72 Mon Sep 17 00:00:00 2001 +From f4636b37ea9c34b2f3fc7efa04fd34fa4b8b2542 Mon Sep 17 00:00:00 2001 From: Sam James <[email protected]> Date: Mon, 25 Dec 2023 16:57:15 +0000 -Subject: [PATCH 7/7] Revert "testsuite: Add more pragma novector to new tests" +Subject: [PATCH 8/8] Revert "testsuite: Add more pragma novector to new tests" This reverts commit 0994ddd86f9c3d829b06009d9e706ff72b07001a. diff --git a/14.0.0/gentoo/README.history b/14.0.0/gentoo/README.history index b3ba265..24aaad3 100644 --- a/14.0.0/gentoo/README.history +++ b/14.0.0/gentoo/README.history @@ -1,3 +1,14 @@ +15 8 Jan 2024 + + U 75_all_Revert-middle-end-explicitly-initialize-vec_stmts-PR.patch + U 76_all_Revert-testsuite-un-xfail-TSVC-loops-that-check-for-.patch + U 77_all_Revert_arm_Add_Advanced_SIMD_cbranch_implementation.patch + + 78_all_Revert_testsuite_add_tests_for_early_break_vectorization.patch + + 79_all_Revert_AArch64_add_implementation_for_vector_cbranch.patch + + 80_all_Revert_middle-end_support_vectorization_of_loops_with_mult.patch + + 81_all_Revert-middle-end-prevent-LIM-from-hoising-vector-co.patch + + 82_all_testsuite_Add_more_pragma_novector_to_new_tests.patch + 14 31 Dec 2023 + 75_all_Revert-middle-end-explicitly-initialize-vec_stmts-PR.patch
