On Sun, 18 Jan 2015 21:44:05 +0100 Michał Górny <mgo...@gentoo.org> wrote:
> Hello, > > I would like to commit the following flags as cpu_flags_x86_desc. > The list combines global USE flags with some local USE flags I've been > able to find. > > > 3dnow - Use the 3DNow! instruction set > 3dnowext - Use the Enhanced 3DNow! instruction set > aes-ni - Enable support for Intel's AES instruction set (aes in > cpuinfo) avx - Adds support for Advanced Vector Extensions > instructions avx2 - Adds support for Advanced Vector Extensions 2 > instructions fma - Use the Fused Multiply Add instruction set > mmx - Use the MMX instruction set > mmxext - Use the Extended MMX instruction set (intersection of > Enhanced 3DNow! and SSE instruction sets) (3dnowext or sse in > cpuinfo) padlock - Use VIA padlock instructions popcnt - Enable > popcnt instruction support sse - Use the SSE instruction set > sse2 - Use the SSE2 instruction set > sse3 - Use the SSE3 instruction set (pni in cpuinfo) > sse4 - Enable SSE4 instruction support > sse4_1 - Enable SSE4.1 instruction support > sse4_2 - Enable SSE4.2 instruction support > sse4a - Enable SSE4a instruction support > ssse3 - Use the SSSE3 instruction set > ewwww... are you aware that these descriptions are close to useless ? 'foo - enable foo' -> thanks for the information I couldn't have guessed... you already have more useful ones available: <flag name="fma3">Enables FMA3 optimizations: AMD processors starting with Piledriver architecture and Intel Haswell based processors or later.</flag> <flag name="fma4">Enables FMA4 optimizations: AMD processors starting with Bulldozer architecture.</flag> <flag name="sse4_2">Enables SSE4.2 optimizations: Nehalem-based Intel Core i7 or later.</flag> <flag name="ssse3">Faster floating point optimization for SSSE3 capable chips (Intel Core 2 and later chips)</flag> and so on... Alexis.
