Peter Stuge wrote: > wireless wrote: >> Or for another (mythical) example: >> We used 2 processors, one running a state machine for directly >> reading an array of 20 bit D/A in sub microsecond fashion, and then >> passed the data (like this) to another processor running RT_linux >> (windRiver or embedded-gentoo)..... > > People plug FPGAs into HyperTransport (FSB used by AMD64) - does that > count?
Yes. Any thing you can share is great. Timing/latency data, issues, pseudo code, system architecture...... what decisions where made and why..... My focus is on the "low latency" aspect and what can be done (how fast) directly under embedded linux (rt, rtai, xeno... whatever tricks) control or by bypassing the rtos all together and bringing in the data via another port/interface. why? and also where folks have had to bypass the rtos because of critical timing/bandwidth issues, or just simple to build a system that is difficult to reverse engineer (FPGA or SOC or asic).... Again, I'm not after sensitive information, just performance numbers and any technical details you can or are willing to share. tia, James
