> AMD XP/MP: 128KB L1 cache (64KB instructions, 64KB data) > +512KB L2 cache > =640KB total cache > > Intel Pentium 4 <= 2GHz: > 8KB L1 data cache > + 12KB L1 instruction cache > +256KB L2 cache > =276KB total cache >
It's 256KB because Intel's cache is inclusive, this the L1 cache information is duplicated in the L2. > Intel Pentium 4 >= 2GHz: > 8KB L1 data cache > + 12KB L1 instruction cache > +512KB L2 cache > =532KB total cache > Same here, it's only 512 KB due to being inclusive. AMD has exclusive cache thus the L1 and L2 don't duplicate the cache data. > Of course, AMD Duron and Intel Celerons are cheaper products with less > chache. > Durons have been discontinued. Celrons have both a crippled cache 1/2 of P4 and crippled Front Side Buss' - only 400 MHz (actually it's a 100 MHz base clock. Data is 4x while instructions are at 100 MHz). Bob -- - QA Curmudgeon. Wacky and bizarre testing(TM) performed while-U-wait. - -- [EMAIL PROTECTED] mailing list
