Deven Lahoti <deywos <at> mit.edu> writes:
> Gentoo has been ported to the RISC-V architecture, which you can run > on an FPGA using Berkeley's free (as in freedom) implementation: > https://github.com/palmer-dabbelt/riscv-gentoo > https://github.com/ucb-bar/rocket-chip All good to know. Have you actually installed Gentoo on a fpga dev-board running any of the open source cores? If so any blog, docs, or other postings or a how? > the 4th annual RISC-V workshop was last week; hopefully the > proceedings will be up soon. Do post if you review them and have favourites or strong recommendations on which ones to look at.... Has anyone using the j-core or any other fpga(gentoo) board been successful at using (hardware) components from opencores.org on such hardware? Is there a repo for Rics-v (SH) extra modules, advance ram (multiport) etc? I did find this reference on the various patent-free similar projects:: https://lwn.net/Articles/647636/ I sure hope the SH-4 core is ready for testing? SMP and multiport ram are of keen interest to me, to port some distributed cluster codes and Distributed File Systems (OrangeFS) for performance testing. Is there a gentoo channel or ML on these patent-free cores, gentoo-emebedded the default channel? Is there a default fpga board the gentoo community is using on these superH/riscv/openrisc projects? SH4 does sound very interesting (with mmu). > deven Thanks very much for your response, James > > http://j-core.org/?HN_20160716
