laforge has uploaded this change for review. (
https://gerrit.osmocom.org/c/pysim/+/35823?usp=email )
Change subject: pylint: transport/serial.py
......................................................................
pylint: transport/serial.py
pySim/transport/serial.py:54:0: C0325: Unnecessary parens after 'if' keyword
(superfluous-parens)
pySim/transport/serial.py:89:0: C0325: Unnecessary parens after 'if' keyword
(superfluous-parens)
pySim/transport/serial.py:225:0: C0325: Unnecessary parens after 'while'
keyword (superfluous-parens)
pySim/transport/serial.py:63:12: R1705: Unnecessary "else" after "return",
remove the "else" and de-indent the code inside it (no-else-return)
pySim/transport/serial.py:106:8: R1720: Unnecessary "elif" after "raise",
remove the leading "el" from "elif" (no-else-raise)
pySim/transport/serial.py:124:12: W0707: Consider explicitly re-raising using
'except Exception as exc' and 'raise ValueError('Invalid reset pin %s' %
self._rst_pin) from exc' (raise-missing-from)
pySim/transport/serial.py:204:12: R1723: Unnecessary "elif" after "break",
remove the leading "el" from "elif" (no-else-break)
pySim/transport/serial.py:20:0: C0411: standard import "import time" should be
placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:21:0: C0411: standard import "import os" should be
placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:22:0: C0411: standard import "import argparse" should
be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:23:0: C0411: standard import "from typing import
Optional" should be placed before "import serial" (wrong-import-order)
Change-Id: I82ef12492615a18a13cbdecf0371b3a5d02bbd5c
---
M pySim/transport/serial.py
1 file changed, 30 insertions(+), 10 deletions(-)
git pull ssh://gerrit.osmocom.org:29418/pysim refs/changes/23/35823/1
diff --git a/pySim/transport/serial.py b/pySim/transport/serial.py
index 06a082a..b4eddcd 100644
--- a/pySim/transport/serial.py
+++ b/pySim/transport/serial.py
@@ -16,11 +16,11 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-import serial
import time
import os
import argparse
from typing import Optional
+import serial
from pySim.exceptions import NoCardError, ProtocolError
from pySim.transport import LinkBase
@@ -51,7 +51,7 @@
self._atr = None
def __del__(self):
- if (hasattr(self, "_sl")):
+ if hasattr(self, "_sl"):
self._sl.close()
def wait_for_card(self, timeout: Optional[int] = None, newcardonly: bool =
False):
@@ -62,8 +62,7 @@
self.reset_card()
if not newcardonly:
return
- else:
- existing = True
+ existing = True
except NoCardError:
pass
@@ -86,7 +85,7 @@
# Tolerate a couple of protocol error ... can happen if
# we try when the card is 'half' inserted
pe += 1
- if (pe > 2):
+ if pe > 2:
raise
# Timed out ...
@@ -105,7 +104,7 @@
rv = self._reset_card()
if rv == 0:
raise NoCardError()
- elif rv < 0:
+ if rv < 0:
raise ProtocolError()
return rv
@@ -120,8 +119,8 @@
try:
rst_meth = rst_meth_map[self._rst_pin[1:]]
rst_val = rst_val_map[self._rst_pin[0]]
- except:
- raise ValueError('Invalid reset pin %s' % self._rst_pin)
+ except Exception as exc:
+ raise ValueError('Invalid reset pin %s' % self._rst_pin) from exc
rst_meth(rst_val)
time.sleep(0.1) # 100 ms
@@ -203,7 +202,7 @@
b = self._rx_byte()
if ord(b) == pdu[1]:
break
- elif b != '\x60':
+ if b != '\x60':
# Ok, it 'could' be SW1
sw1 = b
sw2 = self._rx_byte()
@@ -222,7 +221,7 @@
to_recv = data_len - len(pdu) + 5 + 2
data = bytes(0)
- while (len(data) < to_recv):
+ while len(data) < to_recv:
b = self._rx_byte()
if (to_recv == 2) and (b == '\x60'): # Ignore NIL if we have no
RX data (hack ?)
continue
--
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Gerrit-Project: pysim
Gerrit-Branch: master
Gerrit-Change-Id: I82ef12492615a18a13cbdecf0371b3a5d02bbd5c
Gerrit-Change-Number: 35823
Gerrit-PatchSet: 1
Gerrit-Owner: laforge <[email protected]>
Gerrit-MessageType: newchange
