IEEE standard specify infinities as distinguished from NAN. Not that the
IEEE standard always makes the best choices (semantics of min and max being
the naughtiest ). But to the extent that hardware supoorts toggling what
values trigger failure it should be reasonably toggle -able
For Intel hardware I'll presume only hardware that has sse2 and newer, and
maybe a warm-up or sibling patch would be to excise x87 float support from
the code gen in GHC
Amusingly one intended use for the large space of nan values was to encode
the nature of the computation that created the nan. And this was intended
to be used by language implementors. Not sure if that will be useful.
Anyways, this and the other positive response is encouraging and I'll see
about making the time to dig into this stuff.
Merry friday all!
On Sep 16, 2016 11:40 AM, "Ben Gamari" <b...@smart-cactus.org> wrote:
Carter Schonwald <carter.schonw...@gmail.com> writes:
> Hello All!
> I had some interesting conversations yesterday with a few folks and the
> take away was that I might experiment with adding an off by default rts
> flag that on applicable architectures that makes all floating point
> computations that yield Nans signaling , plus mayve some HS side hooks to
> enable or disable that per green thread if it doesn't harm no fib. Kinda
> like the way green threads track and save / restore the state of the magic
> c error tracking variable
Sounds reasonable to me; debugging floating point issues is certainly a
chore and this could only help. Regarding a per-thread handling I think
we'd certainly need to benchmark. Note that rts/posix/Signals.c already has
some logic to handle SIGFPE, although it has been disabled for over a
decade due to an infinite loop where the handler immediately threw
another FPE. It would be nice to have a solution to this issue; looping
is quite bad.
Do you lump infinities into the class of NaN values? I'm not sure how
much code would fail due to "legitimate" uses of infinity if so.
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