[Ghdl-discuss] locally static and generics

[Ivan Curtis]

I have run into an issue with ghdl which I believe is a bug. I have
included a small example called bug.vhdl to illustrate the problem.

When the code is analysed, I get the following error message:

orion % ghdl -a bug.vhd
bug.vhd:18:16: object subtype is not locally static
ghdl: compilation error

If the port addr is defined with a fixed range, the analysis is
OK. But since the value of the generic is fixed at elaboration time, I
think the sub range addr(1 downto 0) is in fact locally static. VHDL
simili compiles and elaborates OK.

At the moment I am working-around by assigning to a local signal which
has fixed range.

Best regards,
Ivan

-- bug.vhd included below

library ieee;
use ieee.std_logic_1164.all;

entity bug is
  generic (ADDR_SIZE : natural := 4
  );
  port (clk : in std_logic;
        addr : in std_logic_vector(ADDR_SIZE - 1 downto 0);
        data : out std_logic_vector(3 downto 0)
  );
end bug;

architecture expose of bug is
begin
  p1: process (clk)
  begin
    if clk'event and clk = '1' then
      case addr(1 downto 0) is
        when "00"   => data <= "0000";
        when others => data <= "1111";
      end case;
    end if;
  end process p1;
end architecture expose;