On Fri, Jul 28, 2006 at 05:55:27PM +0930, Ivan Curtis wrote: > Please consider the following code fragments > > on the entity of top level: > txgs_fail_i : in std_logic_vector(2 downto 0); > > in the architecture of top level we have: > signal nc_in_port_to_the_tx_control : std_logic_vector (7 downto 0); > ... > nc_in_port_to_the_tx_control <= (0 => txgs_present_i, > 1 => txgs_loaded_i, > 4 downto 2 => txgs_fail_i(2 downto 0), > others => '0'); > > ghdl gives the following error on analysis: > rtl/sampler_top-a-rtl.vhd:174:63: can't match slice with type std_ulogic > rtl/sampler_top-a-rtl.vhd:174:63: (location of slice) > > but if I do: > nc_in_port_to_the_tx_control <= (0 => txgs_present_i, > 1 => txgs_loaded_i, > 2 => txgs_fail_i(0), > 3 => txgs_fail_i(1), > 4 => txgs_fail_i(2), > others => '0'); > > then all is OK. > > Is this a bug in ghdl? No, this is the correct behavior. A slice in an aggregate duplicate a value. The correct usage is: (4 downto 2 => 'U', xx)
Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
