Hi Tristan,
On Thu, 28 Sep 2006 09:48:42 +0200
[EMAIL PROTECTED] wrote:
> Quoting Attila Kinali <[EMAIL PROTECTED]>:
> > Has anyone here ever used ghdl together with a verilog simulator?
> > If so, could you give me a hint how to do that, ie what software
> > you used and how you got the simulator kernels to work together.
> >
> > I'm asking, because i want to implement some modules in vhdl
> > which later should be simulated together with code written in
> > verilog.
>
> unfortunatly this is not yet possible. And at least a huge amount of work!
What would need to be done for this? Maybe i could help.
And do you know of any way to do VHDL/Verilog co-simulation
with OSS tools?
Attila Kinali
--
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
-- Deed of Morred
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