Hello there, I have the following gene.vhdl file, which I used on ModelSim. It compiles successfully and outputs as appropriate.
However with ghdl, I have an infinity loop when I execute ./gene --vcd=gene.vcd. What may cause this loop and perhaps someone can explain to me why so that in the future I won't do the same mistake. Here is my procedure: ghdl -a gene.vhdl ghdl -e gene ./gene --vcd=gene.vcd gene.vhdl ------------------------------------------------------- library IEEE; use IEEE.Std_Logic_1164.all; entity gene is end gene; architecture bench of gene is signal f0,f2,f4,f8 : Std_Logic:='0'; begin f0 <= not(f0) after 10 ns; f2 <= not(f2) after 20 ns; f4 <= not(f4) after 40 ns; f8 <= not(f8) after 80 ns; end bench; --------------------------------------------------- regards, Chitlesh -- http://clunixchit.blogspot.com _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
