A self contained (w/o reference to unisims) version of Mark's testcase
is attached. I get the same with svn61, i.e. bogus std_logic values in
the ghw file, and even a crash:
./test_sync_fifo --trace-signals --trace-processes
... lines omitted ...
.test_sync_fifo(first)[EMAIL PROTECTED](infer_srl).dout(7) 0836C1D8 e8 ---
last_event=-9223372036854775807fs last_active=0ms val='U'; drv='0'
(6) 0836C260 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
(5) 0836C2E8 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
(4) 0836C370 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
(3) 0836C3F8 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
(2) 0836C480 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
(1) 0836C508 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
(0) 0836C590 e8 --- last_event=-9223372036854775807fs last_active=0ms val='U';
drv='0'
.test_sync_fifo(first)[EMAIL PROTECTED](infer_srl).empty 0836BFE0 e8 ---
last_event=30ns last_active=30ns val='1'; drv='1'
.test_sync_fifo(first)[EMAIL PROTECTED](infer_srl).a 0836CA08 i32 AE-
last_event=1030ns last_active=1030ns val=1; drv=1
./test_sync_fifo:error: invalid memory access (dangling accesses or stack size
too small)
.test_sync_fifo(first)[EMAIL PROTECTED](infer_srl).memory(0)(7) 0836CCF8 e8
AE- last_event=1030ns last_active=1030ns val=
Program received signal SIGSEGV, Segmentation fault.
0x00c1959b in strlen () from /lib/libc.so.6
(gdb) bt
#0 0x00c1959b in strlen () from /lib/libc.so.6
#1 0x080898f5 in grt__vstrings__append__3 ()
#2 0x08089fb9 in grt__rtis_utils__get_enum_value ()
#3 0x0808a0f5 in grt__rtis_utils__get_value ()
#4 0x0808a2f3 in grt__rtis_utils__disp_value ()
#5 0x08080801 in grt__disp_signals__disp_simple_signal ()
#6 0x08080a0c in grt__disp_signals__foreach_scalar_signal__handle_scalar.873
()
#7 0x0808287f in grt__disp_signals__foreach_scalar_signal__handle_any.870 ()
#8 0x08082f0d in grt__disp_signals__foreach_scalar_signal__handle_array_1.914
()
#9 0x08082b60 in grt__disp_signals__foreach_scalar_signal__handle_any.870 ()
#10 0x08082f0d in grt__disp_signals__foreach_scalar_signal__handle_array_1.914
()
#11 0x08082b60 in grt__disp_signals__foreach_scalar_signal__handle_any.870 ()
#12 0x08083152 in grt__disp_signals__foreach_scalar_signal ()
#13 0x0808321a in grt__disp_signals__disp_signal ()
#14 0x08083417 in
grt__disp_signals__disp_all_signals__traverse_blocks_1__2.1399 ()
#15 0x0808347c in
grt__disp_signals__disp_all_signals__traverse_instance__2.1396 ()
#16 0x080833e5 in
grt__disp_signals__disp_all_signals__traverse_blocks_1__2.1399 ()
#17 0x0808347c in
grt__disp_signals__disp_all_signals__traverse_instance__2.1396 ()
#18 0x080834cb in grt__disp_signals__disp_all_signals__2 ()
#19 0x080834f3 in grt__disp_signals__disp_all_signals ()
#20 0x0807e8b3 in grt__processes__simulation ()
#21 0x08088fe8 in grt__main__run ()
#22 0x080872fd in ghdl_main ()
#23 0x0808393a in main ()
./test_sync_fifo --dump-rti
gets into an infinite loop...
Tom
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_fifo is
generic(
g_depth: integer:=16; -- The number of words to be stored in the fifo
g_width: integer:=8; -- The width of the input and output data
g_room: integer:=5 -- The number of empty words for "almost_full"
);
port(
clock: in std_logic;
reset: in std_logic;
we: in std_logic;
din: in std_logic_vector(g_width-1 downto 0);
almost_full: out std_logic;
rd: in std_logic;
dout: out std_logic_vector(g_width-1 downto 0);
empty: out std_logic
);
end sync_fifo;
architecture infer_srl of sync_fifo is
signal a: integer range 0 to g_depth;
type memory_v is array(integer range<>) of std_logic_vector(g_width-1 downto 0);
signal memory: memory_v(0 to g_depth):=(others=>(others=>'0'));
function to_std_logic (x : boolean) return std_logic is
begin
if x then
return '1';
end if;
return '0';
end to_std_logic;
begin
almost_full<=to_std_logic(g_depth-a<g_room);
process(clock)
begin
if clock'event and clock='1' then
if reset='1' then
a<=0;
else
empty<=to_std_logic(a=0);
if we='1' then
memory<=din & memory(0 to g_depth-1);
end if;
if we='0' and rd='1' and a>0 then
a<=a-1;
elsif we='1' and rd='0' and a/=g_depth then
a<=a+1;
end if;
end if;
end if;
end process;
dout<=memory(a);
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_sync_fifo is
end;
architecture first of test_sync_fifo is
signal clock: std_logic:='0';
signal reset: std_logic:='1';
signal we: std_logic:='0';
signal din: std_logic_vector(7 downto 0):=(others=>'0');
signal almost_full: std_logic;
signal rd: std_logic:='0';
signal dout: unsigned(7 downto 0);
signal empty: std_logic;
begin
clock<=not clock after 10 ns;
reset<='0' after 30 ns;
dut: entity work.sync_fifo generic map (
g_depth=>16,
g_width=>8,
g_room=>5
) port map (
clock=>clock,
reset=>reset,
we=>we,
din=>din,
almost_full=>almost_full,
rd=>rd,
unsigned(dout)=>dout,
empty=>empty
);
process
begin
wait for 1 us;
loop
wait until rising_edge(clock);
we<='1';
din<=std_logic_vector(unsigned(din)+1);
wait until rising_edge(clock);
we<='0';
end loop;
end process;
end;
_______________________________________________
Ghdl-discuss mailing list
[email protected]
https://mail.gna.org/listinfo/ghdl-discuss
