Hy, I use an IP from open cores (uart16550) written in Verilog, but i don't know Verilog. Then to synthesize it I «packed» the verilog code in VHDL top component. That work with ISE, I can synthesize it.
But is it possible to simulate it with GHDL ? Or do you know if a free software can do that ? Thanks a lot FabM
_______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
