>
> this looks like a mistake from you but it will be more easier to explain
> if you provide a compilable example. In the above exerpt, the first two
> lines are not valid VHDL :-)
>
> Tristan.
>
>
>
In the example below, 3 of the 4 "instanceVector: should be uninitialized,
but they are all uninitialized.
library ieee;
use ieee.STD_LOGIC_1164.all, ieee.NUMERIC_STD.all;
package test_utils is
component one_to_all
generic (
size_o : positive);
port (
theInput : in std_logic; -- bit for "others"
theOutput : out std_logic_vector(size_o - 1 downto 0)); -- others
=> theInput
end component;
end test_utils;
library ieee;
use ieee.STD_LOGIC_1164.all, ieee.NUMERIC_STD.all;
use work.test_utils.one_to_all;
entity one_to_all is
generic (
size_o : positive);
port (
theInput : in std_logic;
theOutput : out std_logic_vector( size_o - 1 downto 0 ));
end one_to_all;
architecture arch_one_to_all of one_to_all is
begin -- arch_one_to_all
theOutput <= ( others => theInput );
end arch_one_to_all;
library ieee;
use ieee.STD_LOGIC_1164.all, ieee.NUMERIC_STD.all;
use work.test_utils.one_to_all;
entity bench_test is
generic (
with_the_cast : boolean := true;
size_o : positive := 6;
nbre_of_elements : positive := 3);
end bench_test;
architecture arch_bench_test of bench_test is
signal counter_int : unsigned( 3 downto 0 ) := "0000"; -- main clk counter
signal counter_max : unsigned( 3 downto 0 ) := "1000"; -- value that
stops the simul
type myVector is array (size_o - 1 downto 0 ) of std_logic;
type myMatrix is array (nbre_of_elements downto 0) of myVector;
signal instanceMatrix : myMatrix;
signal instanceVector0 : myVector;
signal instanceVector1 : myVector;
signal instanceVector2 : myVector;
signal instanceVector3 : myVector;
begin -- arch_bench_test
-- purpose: main process for the demo
-- type : sequential
-- inputs : CLK
-- outputs: the output of the one_in_all entity
theClock: process
begin -- process theClock
if counter_int = counter_max then
wait;
else
counter_int <= counter_int + 1;
wait for 1 ns;
end if;
end process theClock;
ota_instanc : one_to_all generic map (
size_o => size_o)
port map (
theInput => counter_int(1),
-- Here if the cast is removed,
-- error is issued while trying to run ghdl with the -a option :
-- test.vhdl:xyz:7: no interface for 'theoutput' in association
theOutput => std_logic_vector(instanceMatrix(1)));
instanceVector0 <= instanceMatrix(0);
instanceVector1 <= instanceMatrix(1);
instanceVector2 <= instanceMatrix(2);
instanceVector3 <= instanceMatrix(3);
end arch_bench_test;
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