On Thu, Dec 11, 2008 at 11:39 AM, Kendrick Hamilton
<[email protected]> wrote:
> Doxygen is starting to develop for VHDL.

Does doxygen actually read my FSM from VHDL, or does it just take some
comments I make and generate from that?

Since GHDL parses the VHDL, I would think it might be feasible to show
the transitions between states for enumerated types being used within
case statements.

The block diagram would just be a nice feature for documentation generation.

The main issue I have with doxygen is that it's driven by comments and
not by the code.  The code gets analyzed, elaborated and synthesized;
the comments do not.

Brian

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