Quoting Sylvere Teissier <[email protected]>: > Futhermore, if Lattice is a synthesis tool it can check the output > vector length of the "+" operation because a synthesis tool use > techniques like function expansion, loop unrolling and constant > propagation that permit to have more information and more checking. > Theses techniques are only applicable on a subset a VHDL (for example > synthetizable code). > A simulator is more generalist and check result at run-time after "+" > function call. (well known "bound check failed")
Yes, that's correct. Ian, did you expect an error during analysis or at run time ? Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
