Hy, I managed to compile Xilinx library unisim and simprim following this instruction mail : https://mail.gna.org/public/ghdl-discuss/2007-10/msg00016.html
That work well to simulate Bloc of ram using unisim in behavioural simulation, but I have lot of warning and error when I simulate post place & route simulation model (myproject_timesim.vhd) : >ghdl -i --ieee=synopsys -P$XILINX/ghdl/simprim -P$XILINX/ghdl/unisim --warn-no-vital-generic --workdir=simu --work=work top_test_latency_logger_tb.vhd apf_test_pkg.vhd top_test_latency_logger_timesim.vhd >ghdl -m --ieee=synopsys -P$XILINX/ghdl/simprim -P$XILINX/ghdl/unisim --warn-no-vital-generic --workdir=simu --work=work top_test_latency_logger_tb >../../../src/vital2000/timing_b.vhdl:196:15:warning: procedure "vitalerror" is never used >../../../src/vital2000/timing_b.vhdl:217:15:warning: procedure "vitalerror" is never used >../../../src/vital2000/prmtvs_b.vhdl:1041:15:warning: function "toedge" is never used >simprim_vital_chop/x_obuft.vhd:49:7:warning: 'gts' is not a port name (in VITAL generic name) >simprim_vital_chop/x_bufgmux_1.vhd:277:7:warning: 'gsr' is not a port name (in VITAL generic name) >simprim_vital_chop/x_latche.vhd:53:7:warning: 'gsr' is not a port name (in VITAL generic name) >simprim_vital_chop/x_latche.vhd:54:7:warning: 'prld' is not a port name (in VITAL generic name) >top_test_latency_logger_timesim.vhd:15968:3:warning: component instance "latency_measure_connect_nover_s_addsub0000_0_logic_zero" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >[...] >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >top_test_latency_logger_timesim.vhd:19612:3:warning: component instance "latency_measure_connect_tacc_sum_32_logic_zero" is not bound >[...] >top_test_latency_logger_timesim.vhd:20705:3:warning: component instance "latency_cmpt_connect_count_s_0_logic_zero" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >[...] >top_test_latency_logger_timesim.vhd:27856:3:warning: component instance "latency_measure_connect_din_a_addsub0000_0_logic_zero" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >[...] >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >top_test_latency_logger_timesim.vhd:35292:3:warning: component instance "latency_ram_connect_ramb16_s36_s36_inst" is not bound >[...] >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >top_test_latency_logger_timesim.vhd:55991:3:warning: component instance "global_logic0_gnd" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >top_test_latency_logger_timesim.vhd:57103:3:warning: component instance "nlwblock_top_test_latency_logger_gnd" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >simprim_vital_chop/x_bufgmux_1.vhd:41:7:warning: 'gsr' is not a port name (in VITAL generic name) >analyze apf_test_pkg.vhd >analyze top_test_latency_logger_tb.vhd >analyze top_test_latency_logger_timesim.vhd >elaborate top_test_latency_logger_tb >top_test_latency_logger_timesim.vhd:15968:3:warning: component instance "latency_measure_connect_nover_s_addsub0000_0_logic_zero" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) >[...] >top_test_latency_logger_timesim.vhd:29332:3:warning: component instance "latency_measure_connect_din_a_addsub0000_22_logic_zero" is not bound >top_test_latency_logger_timesim.vhd:52:14:warning: (in default configuration of top_test_latency_logger(structure)) And when I run simulation I've a simulation error : >simu/top_test_latency_logger_tb:error: NULL access dereferenced >simu/top_test_latency_logger_tb:error: simulation failed >make: *** [ghdl-run] Erreur 1 Does somebody has already experimented post place and route simulation ? Thanks a lot for all your help. Fabien Marteau Hardware Engineer +33 (0)3 89 70 89 24 ARMadeus Systems - A new vision of the embedded world http://www.armadeus.com
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