> Hmmm ... LEON isn't a good example of normal VHDL coding. Gaisler used a 
> special technique to code LEON, this technique is very different to 
> regular VHDL coding.

The PDF from Jiri Gaisler which I ran across in the last week or so, seems to 
suggest that this 2 process coding style that he used for LEON2 is a definite 
win across a number of metrics.

So while it may not be typical VHDL coding, perhaps it should be.

> A paper (included in a chapter of LEON docs) 
> explains it. Is something like this: blocks get in/out records 
> containing all the I/O. One process determines the next state from the 
> current and the I/O. Another process transfers the next state to the 
> current and sets the outputs.

Can you please provide a URL, if it goes into more detail than the PDF I 
reference below? I think this particular coding style from Gaisler is worth 
digging into.

It reminds me of a VHDL analogy to OOP design patterns, ie a particular 
methodology for writing VHDL to improve its readability and maintainability and 
lower development time.

> According to Gaisler it allows for a much higher abstraction. We tried 
> to apply this technique with mixed results, usually involving slower 
> simulation as the portions recoded like this increased.

I was wondering if this is what you're referring to:

http://www.gaisler.com/doc/structdes.pdf

A comment on this two-process VHDL style slowing simulation. On GHDL it might 
very well be slower, until GHDL is further refined. But if one factors in a 
long lifecycle for VHDL as comparable to Ada projects, ie. 10-20 years, the 
human-centric gains for maintaining a large VHDL codebase in this way might be 
a significant win versus some percentage slower RTL simulation, whatever that 
percentage might be, I suspect less than 20% at the most.

After all, Jiri Gaisler implemented an entire SPARC core for the European Space 
Agency. I would give this technique some leeway on those grounds.


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