Hello,
Thanks for your reply. It was really helpful and it works now.
Do you have any idea how to do also post-map simulation? I've tried the same
thing using simprim:
ghdl -i --work=simprim simprim/*.vhd
ghdl -i --work=simprim simprim/primitive/other/*.vhd
ghdl -i *.vhd
ghdl -m -g --warn-unused --ieee=synopsys temp_tb
This is what I get after the last command:
../../../src/vital2000/timing_b.vhdl:196:15:warning: procedure "vitalerror" is
never used
../../../src/vital2000/timing_b.vhdl:217:15:warning: procedure "vitalerror" is
never used
../../../src/vital2000/prmtvs_b.vhdl:1041:15:warning: function "toedge" is
never used
simprim/other/X_BUF.vhd:35:5:warning: generic "loc" is not a VITAL generic
simprim/other/X_BUF.vhd:41:5:warning: generic "pathpulse" is not a VITAL generic
simprim/other/X_OBUF.vhd:41:7:warning: generic "capacitance" is not a VITAL
generic
simprim/other/X_OBUF.vhd:42:7:warning: generic "drive" is not a VITAL generic
simprim/other/X_OBUF.vhd:43:7:warning: generic "iostandard" is not a VITAL
generic
simprim/other/X_OBUF.vhd:44:7:warning: generic "loc" is not a VITAL generic
simprim/other/X_OBUF..vhd:45:7:warning: generic "slew" is not a VITAL generic
simprim/other/X_OBUF.vhd:50:7:warning: generic "pathpulse" is not a VITAL
generic
simprim/other/X_BUFGMUX.vhd:43:5:warning: generic "clk_sel_type" is not a VITAL
generic
simprim/other/X_BUFGMUX.vhd:44:5:warning: generic "loc" is not a VITAL generic
simprim/other/X_BUFGMUX.vhd:46:7: clock port name of 'ticd' VITAL generic must
not appear here
simprim/other/X_BUFGMUX.vhd:47:7: clock port name of 'ticd' VITAL generic must
not appear here
simprim/other/X_BUFGMUX.vhd:73:7: clock port name of 'ticd' VITAL generic must
not appear here
simprim/other/X_BUFGMUX.vhd:74:7: clock port name of 'ticd' VITAL generic must
not appear here
make: *** [nbitcounter] Error 1
Thanks again,
Mihai
________________________________
From: René Doß <[email protected]>
To: GHDL discuss list <[email protected]>
Sent: Fri, January 29, 2010 8:47:00 PM
Subject: Re: [Ghdl-discuss] GHDL & Xilinx - need help
Hallo,
I prefer to import your vhdl files and the unisim files in ghdl.
For short time I wrote a paper about this topic.
Look at http://www.dossmatik.de/ghdl/ghdl_unisim_eng.pdf
The second improved example is simulated with unisim.
René Doß
Am Freitag, den 29.01.2010, 06:20 -0800 schrieb lefter mihai:
> Hello everyone,
>
> I'm trying to simulate some Xilinx VHDL design with GHDL.
> Unfortunately I have some problems. I am using GHDL 0.28 and Xilinx
> Webpack 11.3. Here is how I try to do it.
>
> I got the post-synthesis file - 'temp_synthesis.vhd' which starts like
> this:
> ....
> library UNISIM;
> use UNISIM.VCOMPONENTS.ALL;
> use UNISIM.VPKG.ALL;
> ...
>
> I've copied the 'unisim_VCOMP.vhd' and 'unisim_VPKG.vhd' files
> from .../Xilinx/11.1/ISE/vhdl/src/unisims into a new created folder.
> I've added there also the 'temp_synthesis.vhd" and the test bench
> ('temp_tb.vhd'). I've also created the unisim and work subfolders.
>
> Now the commands that I use:
>
> $ghdl -a --work=unisim --workdir=unisim --ieee=synopsys -fexplicit
> unisim_VCOMP.vhd
> OK
>
> $ghdl -a --work=unisim --workdir=unisim --ieee=synopsys -fexplicit
> unisim_VPKG.vhd
> OK
>
> $ghdl -a --work=work -Punisim --workdir=work --ieee=synopsys
> -fexplicit temp_synthesis.vhd
> OK
>
> $ghdl -a --work=work -Punisim --workdir=work --ieee=synopsys
> -fexplicit temp_tb.vhd
> OK
>
> Here comes the problem. When I do:
>
> $ghdl -m --work=work -Punisim --workdir=work --ieee=synopsys
> -fexplicit temp_tb
>
> I get a lot of warnings like:
> ...
> temp_synthesis.vhd:56:14:warning: (in default configuration of
> temp(structure))
> temp_synthesis.vhd:5031:3:warning: component instance
> "so_rout_mask_3_and00001" is not bound
> temp_synthesis.vhd:56:14:warning: (in default configuration of
> temp(structure))
> temp_synthesis.vhd:5041:3:warning: component instance
> "so_rout_mask_2_and00011" is not bound
> temp_synthesis.vhd:56:14:warning: (in default configuration of
> temp(structure))
> temp_synthesis.vhd:5051:3:warning: component instance
> "so_rout_mask_2_and00001" is not bound
> temp_synthesis.vhd:56:14:warning: (in default configuration of
> temp(structure))
> ...
> temp_synthesis.vhd:56:14:warning: (in default configuration of
> temp(structure))
> temp_synthesis.vhd:6745:3:warning: component instance
> "state_fsm_ffd1_in_sw1" is not bound
> ...
>
> It looks like no component is bound. What do the warnings mean? Any
> clue about possible solutions? My objective is to find out whether
> it's possible to perform timing simulations with GHDL & Xilinx. Can
> anyone enlighten me?
>
> Thanks,
> Mihai
>
> _______________________________________________
> Ghdl-discuss mailing list
> [email protected]
> https://mail.gna.org/listinfo/ghdl-discuss
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