A problem is appeared with the DCM at the german discussion board.
http://www.mikrocontroller.net/topic/139345#new
First the user had some problem to include all files.
I had supported and this is solved.
The code is stripped and has a reproducer state.
Now are three different variants of DCM to simulate:
rene_dcm.vhd this is running DCM also used in my tutorial
berndl_dcm.vhd this is a new implementation and is out of
working, but runs in fitted code in hardware and Modelsim
xil_wiz_dcm.vhd this is generated code from wizard
and the last a testbench for this application.
My intention is a miss sensitive list in unisim DCM. Or have you other
ideas what is the problem?
Or better how can run tis code correctly?
Modelsim can handle this code. ;-<
René Doß
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; -- RAM, DCM
use UNISIM.VComponents.all;
entity berndl_dcm is
Port ( clk : in std_logic;
clk100_out : out std_logic
);
end berndl_dcm;
architecture Behavioral of berndl_dcm is
signal clkbuf : std_logic; --
oscillator clock buffered by IBUFG
signal clkdcm : std_logic;
-- DCM output clock going to BUFG
signal clk100 : std_logic;
-- FPGA clock, 100MHz, from BUFG
signal dcm_locked : std_logic := '0'; -- indicate that DCM
has locked to target frequency
begin
clk100_out <= clk100;
IBUFG_inst : IBUFG
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => clkbuf, -- Clock buffer output
I => clk -- Clock buffer input (connect directly
to top-level port)
);
BUFG_inst : BUFG
port map (
O => clk100, -- Clock buffer output
I => clkdcm -- Clock buffer input
);
DCM_inst : DCM generic map (
CLKDV_DIVIDE => 2.5, -- Divide by:
1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or
16.0
CLKFX_DIVIDE => 1, -- Can be any interger
from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer
from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN
divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED
or VARIABLE
-- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X
or 2X
CLK_FEEDBACK => "2X", -- Specify clock feedback of NONE, 1X
or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS,
SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for
frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => FALSE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift
from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration
DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => open, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => clkdcm, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcm_locked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clk100, -- DCM clock feedback
CLKIN => clkbuf, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust
increment/decrement
RST => '0' -- DCM asynchronous reset input
);
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY dcm_test_tb IS
END dcm_test_tb;
ARCHITECTURE behavior OF dcm_test_tb IS
component rene_dcm
port (
clk50_in : in std_logic;
clk75_rene_out : out std_logic
);
end component;
component berndl_dcm
port (
clk : in std_logic;
clk100_out : out std_logic
);
end component;
component xil_wiz_dcm
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end component;
--Inputs
signal clk50_in : std_logic := '0';
--Outputs
signal clk75_rene_out : std_logic;
signal clk100_berndl_out : std_logic;
signal xil_wiz_rst_in : std_logic := '0';
signal xil_wiz_clkin_ibufg_out : std_logic;
signal xil_wiz_clk2x_out : std_logic;
signal xil_wiz_locked_out : std_logic;
-- Clock period definitions
constant clk50_in_period : time := 20 ns;
BEGIN
uut_rene : rene_dcm port map (
clk50_in => clk50_in,
clk75_rene_out => clk75_rene_out
);
uut_berndl : berndl_dcm port map (
clk => clk50_in,
clk100_out => clk100_berndl_out
);
uut_xil_wiz : xil_wiz_dcm port map (
CLKIN_IN => clk50_in,
RST_IN => xil_wiz_rst_in,
CLKIN_IBUFG_OUT => xil_wiz_clkin_ibufg_out,
CLK2X_OUT => xil_wiz_clk2x_out,
LOCKED_OUT => xil_wiz_locked_out
);
clk50_in_process : process
begin
clk50_in <= '0';
wait for clk50_in_period/2;
clk50_in <= '1';
wait for clk50_in_period/2;
end process;
END;
library IEEE;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity rene_dcm is
port(
clk50_in : in std_logic;
clk75_rene_out : out std_logic
);
end rene_dcm;
architecture behavioral of rene_dcm is
signal clk75 : std_logic;
signal CLK0_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
clk75_rene_out <= CLK75;
GND_BIT <= '0';
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLK50_in,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLK75);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>'0',
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end behavioral;
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 10.1.03
-- \ \ Application : xaw2vhdl
-- / / Filename : tmp_dcm.vhd
-- /___/ /\ Timestamp : 10/29/2010 07:45:44
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st D:\vhdl_uc\tmp_dcm_wizard\tmp_dcm.xaw
D:\vhdl_uc\tmp_dcm_wizard\tmp_dcm
--Design Name: tmp_dcm
--Device: xc3s200-ft256-4
--
-- Module tmp_dcm
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity xil_wiz_dcm is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end xil_wiz_dcm;
architecture BEHAVIORAL of xil_wiz_dcm is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK2X_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK2X_OUT <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK2X_BUFG_INST : BUFG
port map (I=>CLK2X_BUF,
O=>CLKFB_IN);
DCM_INST : DCM
generic map( CLK_FEEDBACK => "2X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"8080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>open,
CLK2X=>CLK2X_BUF,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
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