Hello
I need your opinion about my interpretation of the following GHDL
simulation.
The design is a single-port ram with SYNCHRONOUS read.
The testbench simply write 5 data (85..89) at (0..4), and then read the
data in the same order.
The gtkwave waveforms are perfectly ok w.r.t my expectations.
My problem is about the text in the terminal :
test_mem.vhd:70:5:@390ns:(report note): 20-reading memory
test_mem.vhd:73:7:@390ns:(report note): 20-address 0
test_mem.vhd:78:7:@410ns:(report note): 21-READ data dout 89
test_mem.vhd:73:7:@410ns:(report note): 21-address 1
test_mem.vhd:78:7:@430ns:(report note): 22-READ data dout 85
test_mem.vhd:73:7:@430ns:(report note): 22-address 2
test_mem.vhd:78:7:@450ns:(report note): 23-READ data dout 86
test_mem.vhd:73:7:@450ns:(report note): 23-address 3
test_mem.vhd:78:7:@470ns:(report note): 24-READ data dout 87
test_mem.vhd:73:7:@470ns:(report note): 24-address 4
test_mem.vhd:78:7:@490ns:(report note): 25-READ data dout 88
We see that at cycle 20 address=0 is generated. ok.
One cycle later (21), I expected to get the data 85 (as in the
waveform), but here the message says 89.
Where am I wrong ?
Thx
JCLL
[timestart] 0
[size] 1680 980
[pos] -1 -1
*-27.498905 279700000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.test_mem.
[treeopen] top.test_mem.dut.
@28
top.test_mem.we
top.test_mem.clk
top.test_mem.doit
@22
#addr[4:0] top.test_mem.dut.addr[4] top.test_mem.dut.addr[3]
top.test_mem.dut.addr[2] top.test_mem.dut.addr[1] top.test_mem.dut.addr[0]
#addr_reg[4:0] top.test_mem.dut.addr_reg[4] top.test_mem.dut.addr_reg[3]
top.test_mem.dut.addr_reg[2] top.test_mem.dut.addr_reg[1]
top.test_mem.dut.addr_reg[0]
@421
#din[7:0] top.test_mem.din[7] top.test_mem.din[6] top.test_mem.din[5]
top.test_mem.din[4] top.test_mem.din[3] top.test_mem.din[2] top.test_mem.din[1]
top.test_mem.din[0]
@420
#dout[7:0] top.test_mem.dout[7] top.test_mem.dout[6] top.test_mem.dout[5]
top.test_mem.dout[4] top.test_mem.dout[3] top.test_mem.dout[2]
top.test_mem.dout[1] top.test_mem.dout[0]
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use STD.textio.all;
entity test_mem is
end;
architecture tb of test_mem is
signal doit : boolean := true;
signal clk : std_logic := '0';
signal addr : std_logic_vector(4 downto 0);
signal din : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
signal we : std_logic;
begin
DUT : entity work.xilinx_ram_sync(syn)
generic map(
ADDR_WIDTH => 5,
DATA_WIDTH => 8)
port map(
clk => clk,
we => we,
addr => addr,
din => din,
dout => dout
);
clk <= not(clk) after 10 ns when (doit) else clk;
stimuli : process
variable addr_v : unsigned(4 downto 0) := "00000";
variable data_v : signed(7 downto 0) := "00000000";
variable cycle : integer := 0;
procedure wait_cycles (nbCycl : integer) is
begin
for i in 0 to nbCycl-1 loop
wait until rising_edge(clk);
end loop;
cycle := cycle+nbCycl;
end procedure;
begin
we <= '0';
wait_cycles(10);
report integer'image(cycle) & "-writing memory";
data_v := to_signed(85, 8);
addr_v := to_unsigned(0, 5);
for i in 1 to 5 loop
report "address =" & integer'image(to_integer(unsigned(addr_v)));
report "WRITE data din =" & integer'image(to_integer(signed(data_v)));
we <= '1';
addr <= std_logic_vector(addr_v);
din <= std_logic_vector(data_v);
addr_v := addr_v+1;
data_v := data_v+1;
wait_cycles(1);
end loop;
we <= '0';
wait_cycles(5);
report "";
report integer'image(cycle) & "-reading memory";
addr_v := "00000";
for i in 1 to 5 loop
report integer'image(cycle) & "-address "&
integer'image(to_integer(unsigned(addr_v)));
addr <= std_logic_vector(addr_v);
addr_v := addr_v+1;
wait for 0 ns;
wait_cycles(1);
report integer'image(cycle) & "-READ data dout " &
integer'image(to_integer(signed(dout)));
end loop;
wait_cycles(1);
doit <= false;
wait;
end process stimuli;
end tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xilinx_ram_sync is
generic (
ADDR_WIDTH : integer := 12;
DATA_WIDTH : integer := 8);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end xilinx_ram_sync;
architecture syn of xilinx_ram_sync is
type ram_type is array(2**ADDR_WIDTH-1 downto 0) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal ram : ram_type;
signal addr_reg : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
ram(to_integer(unsigned(addr))) <= din;
end if;
addr_reg <= addr;
end if;
end process;
dout <= ram(to_integer(unsigned(addr_reg)));
end syn;
run:
ghdl -a xilinx_ram_sync.vhd
ghdl -a test_mem.vhd
ghdl -a test_mem.vhd
ghdl -e test_mem
ghdl -r test_mem --wave=test_mem.ghw
gtkwave test_mem.ghw test_mem.gtk.sav
clean:
rm -rf *.o_______________________________________________
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