On Wed, 2 Feb 2011 09:53:28 +0100, Benjamin BRAGA
<[email protected]> wrote:
Hi,
I have found the problem (I think). The problem occurs when I am
using variable such like that :
variable_foo := '1';
if foo = '0' then
variable_foo := '0';
end if;
=> doesn't work
The simulation stopped at the beginning with "invalid memory access"
if foo = '0' then
variable_foo := '0';
else
variable_foo := '1';
end if;
=> work
that's WEIRD
BUT this code isn't in initialisation code.
so a wider context is needed...
could you provide a whole minimal VHDL source code file ?
Thanks
I hope i can help,
yg
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