Svenn Are Bjerkem wrote:
> Hi,
>
> I am running a ghdl simulation of mc8051 and want to do some profiling
> by using textio to write the program counter to file. I have found by
> searching google that it is not possible to do this since the program
> counter is a couple of levels down in the hierarchy. I have so far
> used gtkwave on the ghw file and exported to vcd and used vcd2txt to
> get something I can use awk on. Problem is only that the PC shows up
> both on positive and negative edge of the clock, hence the wish to use
> textio to only print on rising clk edge. Ok, that's the background,
> now the question: How do I do this with vpi? I have not tried vpi
> before, and the examples did not make it crystal clear to me how to
> proceed.
Hi all,
not being able to read from test bench a signal 'a couple of levels down
in the hierarchy' is an old nuisance in VHDL and was addressed in VHDL-2008.
The 2008 language version supports
Hierarchical names
which mediate access to sigals and shared variable by absolute or relative path
name.
Other changes which greatly simplify using VHDL in practice are
New condition operator, ?? ( like C ?:)
else and case for generates
process(all) (makes all read signals part of the sensitivity
list)
Also is VHPI now part of the language definition and the semantics defined.
So I wonder whether there is any plan to implement some of the
new VHDL-2008 language features in ghdl at some point.
With best regards, Walter
> I can, of course, add some buses up to top level and then achieve my
> goal, but if vpi can save me from modifying the design, it would be a
> better solution.
>
> --
> Svenn
>
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