Hi all,

I'm porting over simulations to GHDL and run into an obscure problem: I
am using the floating_point_v4_0.vhd core from the XilinxCoreLib.
The simulation "crashes" from the beginning:

ghdl -r fp_tb --stop-time=10us --wave=fp_tb.ghw
../../../src/synopsys/std_logic_arith.vhdl:2024:16:@0ms:(assertion
warning): CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, and it has been converted to 0.

< more of similar warnings>

./fp_tb:error: bound check failure at
../../../src/synopsys/std_logic_arith.vhdl:334
./fp_tb:error: simulation failed
/usr/lib/ghdl/bin/ghdl: compilation error

I've done done tracing with GDB, it turns out a std_logic_vector has
illegal values (i.e. > 7) in the BASE array which makes the IS_X()
function in the std_logic_arith fail.
So far I have been avoiding std_logic_arith, but the Xilinx code depends
on it.

I've also tried tracing stuff inside the loating_point_v4_0_xst.vhd file
by just printing out values. It seems the values get assigned right and
have legal, but from the GDB side it can be seen that they suddenly
become garbage. --stack-size doesn't change anything.

Is this allowed that SLV values become undefined, or is this a bug?
I've tried v0.28 and v0.29 with same behaviour.

I've posted a tgz (Linux) to reproduce the error:

http://section5.ch/tmp/fptest.tgz

You need a Xilinx Webpack distribution. I guess the licenses of the
xilinx .vhd's wouldn't allow me to include them here.

Greetings,

- Martin


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