2011/11/20 David Koontz <[email protected]>: >> This is clearly a bug. > > I'm afraid to see your resolution function with 3 or more elements in a > record. I've seen Ben Cohen's book Real chip design and verification using > Verilog and VHDL and am aware of Jim Lewis wanting to do introspection. The > idea being to have some set of default functions for dealing with record > elements instead of making the VHDL code author grow their own. Integers do > seem a little extreme.
Actually, it was popped during testing our internal VHDL translator against GHDL. So it is artifical example but I felt I have to inform developers about it. Also, my friends told me that other VHDL simulators analyze this test just fine. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
