Hallo,
picking up on the recent thread 'postfitting timing simulation with XIlinx'
a few remarks on using ghdl together with the Xilinx ISE tool chain:
- Building Xilinx unisim and simprim for ghdl
The Xilinx unisim and simprim libraries 'mostly' compile, over the
years there were always problems with a few modules not compiling or
not working. I wrote two little scripts (both attached)
xilinx_ghdl_unisim
xilinx_ghdl_simprim
which create ghdl libraries under
$XILINX/ghdl/unisim
$XILINX/ghdl/simprim
That makes the handling of multiple ISE versions also easy for ghdl
simulations.
Between ISE 11.2 and 13.2 the module
DCM_CLKGEN
failed to compile for unisim as well as simprim. This is finally fixed
in ISE 13.3. The reason was an illegal VHDL construct (arithmetic
with mixed types, which is not allowed in VHDL) which is apparently
tolerated by most commercial VHDL simulators, but not accepted by ghdl.
- Simulations of DCM's
This is known to be unstable at best. Between November 2009 and November
2010 several postings on ghdl-discuss touched in this, look for the
threads
Xilinx Unisim DCM is not working.in GHDL
DCM from Xilinx unisim
My experience as of ISE 13.1 is that in general no output clock is
generated and that models with DCM's fail to work, and as far as I
know the issue was never resolved.
- post-xst and post-par simulations
Apart from DCM's post synthesis (unisim) and post par (simprim) models
worked fine for me in many cases, I use that intensively for the w11
project which is now on opencores, see
http://opencores.org/project,w11
This project also contains a quite elaborated 'make' system which allows
to control ISE synthesis as well as build of ghdl and ISE ISim
simulations (functional as well as post-xst and post-par) from a common
set of descriptor files. This is briefly described in
http://opencores.org/project,w11,implementation
under the section 'The Build System'.
- Running models with very many processes
post-par models tend to have a large number of VHDL processes. The
limiting factor on 32 bit systems is the allocation of stacks. Since
the simprim model processes need very little stack space running ghld
with
--stack-max-size=16384
helps a great deal (Note that this is the per-process stack size).
On Linux there is in addition a limit of 'map' calls, increasing it
with
echo 131072 > /proc/sys/vm/max_map_count
(as root) helps to run very large models. For more on that see the
thread
maximum number of processes in ghdl
on ghdl-discuss in November 2007. This way I've run models with
Number of simple signals: 64956
Number of processes: 52483
Number of sensitized processes: 14861
- Running post-par models with ISE generated timing annotation
Doesn't work as of ghdl 0.29 and ISE 13.3. This is a very old issue,
known since ghdl 0.21, see thread
SDF Backannotation -> doesn't work for Xilinx ISE generated post par models
on ghdl-discuss in July 2007. Unfortunately all written there still
holds, one gets an error like
tb_x:error: x_tsim.sdf:9:16: ':' (colon) expected
and ghdl aborts. ghdl doesn't accept the sdf files generated by the ISE
tool chain.
With best regards, Walter
#!/bin/sh
# $Id: xilinx_ghdl_simprim 248 2009-11-08 22:51:38Z mueller $
#
# Revision History:
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
# 2007-10-26 92 1.0 Initial version
#
if [ -z "$XILINX" ]
then
echo "XILINX not defined"
exit 1
fi
#
cd $XILINX
echo "============================================================"
echo "* Build ghdl SIMPRIM libs for $XILINX"
echo "============================================================"
#
if [ ! -d ghdl ]
then
mkdir ghdl
fi
#
cd $XILINX/ghdl
if [ ! -d simprim ]
then
mkdir simprim
fi
#
cd $XILINX/ghdl/simprim
cp $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd .
cp $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd .
#
# for ISE 11.1 the VITAL models are individually in sub-dir primitives
# and vhdl_analyze_order is a file with best compilation order
# for ISE 10 and before all VITAL models are in one concatenetaed file
# in this case xilinx_vhdl_chop will chop this into individual model files
#
if [ ! -d primitive ]
then
mkdir primitive
fi
cd primitive
#
if [ -d $XILINX/vhdl/src/simprims/primitive ]
then
cp -p $XILINX/vhdl/src/simprims/primitive/other/*.vhd .
cp -p $XILINX/vhdl/src/simprims/primitive/other/vhdl_analyze_order .
else
xilinx_vhdl_chop $XILINX/vhdl/src/simprims/simprim_VITAL.vhd
find . -maxdepth 1 -name "*.vhd" | perl -p -e 's|\./||' > vhdl_analyze_order
fi
#
xilinx_vhdl_memcolltype_fix
#
cd ..
echo "# ghdl ... simprim_Vcomponents.vhd"
ghdl -a --ieee=synopsys --work=simprim --no-vital-checks simprim_Vcomponents.vhd
echo "# ghdl ... simprim_Vpackage.vhd"
ghdl -a --ieee=synopsys --work=simprim --no-vital-checks simprim_Vpackage.vhd
for file in `cat primitive/vhdl_analyze_order`
do
echo "# ghdl ... primitive/$file"
ghdl -a -fexplicit --ieee=synopsys --work=simprim \
--no-vital-checks primitive/$file 2>&1 |\
tee primitive/$file.ghdl.log
done
#
echo "--- scan for compilation errors:"
find primitive -name "*.ghdl.log" | xargs grep error
#
#!/bin/sh
# $Id: xilinx_ghdl_unisim 248 2009-11-08 22:51:38Z mueller $
#
# Revision History:
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
# 2007-10-26 92 1.0 Initial version
#
if [ -z "$XILINX" ]
then
echo "XILINX not defined"
exit 1
fi
#
cd $XILINX
echo "============================================================"
echo "* Build ghdl UNISIM libs for $XILINX"
echo "============================================================"
#
if [ ! -d ghdl ]
then
mkdir ghdl
fi
#
cd $XILINX/ghdl
if [ ! -d unisim ]
then
mkdir unisim
fi
#
cd $XILINX/ghdl/unisim
cp $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd .
cp $XILINX/vhdl/src/unisims/unisim_VPKG.vhd .
#
# for ISE 11.1 the VITAL models are individually in sub-dir primitives
# and vhdl_analyze_order is a file with best compilation order
# for ISE 10 and before all VITAL models are in one concatenetaed file
# in this case xilinx_vhdl_chop will chop this into individual model files
#
if [ ! -d primitive ]
then
mkdir primitive
fi
cd primitive
#
if [ -d $XILINX/vhdl/src/unisims/primitive ]
then
cp -p $XILINX/vhdl/src/unisims/primitive/*.vhd .
cp -p $XILINX/vhdl/src/unisims/primitive/vhdl_analyze_order .
else
xilinx_vhdl_chop $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
find . -maxdepth 1 -name "*.vhd" | perl -p -e 's|\./||' > vhdl_analyze_order
fi
#
xilinx_vhdl_memcolltype_fix
#
cd ..
echo "# ghdl ... unisim_VCOMP.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd
echo "# ghdl ... unisim_VPKG.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd
for file in `cat primitive/vhdl_analyze_order`
do
echo "# ghdl ... primitive/$file"
ghdl -a -fexplicit --ieee=synopsys --work=unisim \
--no-vital-checks primitive/$file 2>&1 |\
tee primitive/$file.ghdl.log
done
#
echo "--- scan for compilation errors:"
find primitive -name "*.ghdl.log" | xargs grep error
#
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